Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Abstract: A method for fabricating a capacitor is provided that can reduce the number of CMP processes. It avoids the use of a CMP process on an uneven interlayer insulating layer on which a storage node is to be formed, by employing a process of forming a sacrificial oxide layer on the uneven interlayer insulating layer, forming a CMP stopper layer, forming another oxide layer, etching the deposited layers until a top surface of uneven interlayer insulating layer is exposed to form a trench therein for a storage node, depositing a conductive material in the trench and on the another oxide, and performing a CMP process until a top surface of the CMP stopper layer is exposed to electrically separate each storage node from another. The remainder of the oxide layer on the CMP stopper layer is then removed and then the CMP stopper layer is removed.

Abstract: In a semiconductor device fabricating process, a copper-based metal film is formed on an insulating layer, and an insulating film is formed on the copper-based metal film. A patterned resist film is formed on the insulating film, and the insulating film is dry-etched using the patterned resist film as a mask to form a hole penetrating through the insulating film. Thereafter, a plasma treatment using an non-oxidizing gas is carried out, and furthermore, a wet treatment using a resist remover liquid is carried out, for removing the resist film and a resist surface hardened layer which was generated in the dry-etching.

Abstract: A method of fabricating a non-perforate suspended platform on a bonded-substrate is disclosed. The method includes forming a dielectric layer on a support surface of a base substrate followed by patterning an interface surface of the dielectric layer to define a well feature. The well feature is etched until a well having a depth that leaves a thin protective layer of the dielectric layer covering the support surface. Next a platform substrate is urged into contact with the base substrate followed by annealing the base and platform substrates to fusion bond the interface surface with a mounting surface of the platform substrate. The platform substrate is thinned, to form a membrane over a sealed cavity defined by the well and the mounting surface. The membrane is patterned and etch to form a plurality of trenches that extend through the membrane to the sealed cavity and define a suspended platform and a flexure.

Abstract: Lead brass components for potable water distribution circuits (e.g., plumbing components made of CuZn39Pb3, containing 3% Pb), also chronium plated ones, are subjected to a lead-selective surface etching to reduce, in operation, the release of Pb caused by Pb surface “smearing”, resulting either from machining or molding; said elements are firstly contacted by an aqueous solution of an acid capable of forming soluble Pb salts, preferably a non-oxidizing solution, by simply dipping the components in the solution, e.g., a solution of 0.1 M sulfamic acid, at 20°−50° C. for 10 to 50 minutes, and, subsequently, the elements are passivated by immersion into a strong base aqueous solution, e.g., a solution of 0.1 M NaOH at 20°−25° C., for approximately 10 minutes; in this manner, plumbing components made of a copper based alloy containing Pb are obtained, which components, after 15 days of test according to US NSF STD61 procedure, release Pb in an amount less than 0.

Abstract: A method for etching an insulating layer in a semiconductor device includes forming an insulating layer, such as silicon oxide or silicon nitride layer, on a semiconductor substrate and dry etching the insulating layer using a reactive gas including Ar, and C4HxF8-xO, wherein x is an integer from 0 to 4. The reactive gas may further include oxygen gas.

Abstract: A process for preparing doped molten silicon for use in a single silicon crystal growing process is disclosed. Polysilicon is doped with barium and melted in a silica crucible containing less than about 0.5% gases insoluble in silicon. During melting and throughout the crystal growing process the barium acts as a devitrification promoter and creates a layer of devitrified silica on the inside crucible surface in contact with the melt resulting in a lower level of contaminants in the melt and grown crystal.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used because no additional resist is required to provide a “margin of error” during the etching to assure the integrity of the barrier layer. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.

Abstract: The pelletized product of melt condensation polymerization of 1,3-propanediol and terephthalic acid is crystallized in a vessel designed for continuous fluidized bed flow of the pellets in water at a temperature within the range of about 65 to about 100° C. Hot-water treatment in the vessel permits crystallization of the pellets in a continuous operation and results in an increase of the crystallinity of the polymer to greater than about 35% and an increase in pellet density.

Abstract: A method for dry plasma selective etching of a pattern in a silicon nitride dielectric layer formed over a semiconductor substrate employed within a microelectronics fabrication. There is provided a semiconductor substrate having formed thereupon a pad oxide layer over which is formed a silicon nitride dielectric layer. There is formed over the substrate a patterned photoresist etch mask layer. There is then selectively etched the pattern of the photoresist etch mask layer into the silicon nitride layer employing a four-step etching process with three plasma etching environments which include; (1) a “break-through” etching step; (2) a “bulk” etching step to remove a majority of the silicon nitride layer and a “buffer” etching step to remove the remainder of the silicon nitride layer; and (3) an “over-etch” step to complete removal of silicon nitride without excessive etching of underlying material.

Abstract: A method for forming high quality oxide layers having different thicknesses by eliminating descum induced defects is disclosed. A semiconductor substrate is subjected to reactive ion etching. The semiconductor substrate includes a wafer, an oxide layer on the wafer, a developed photoresist mask on the oxide layer. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.

Abstract: A method of etching a tungsten film, comprising the steps of supporting a semiconductor substrate having a tungsten film thereon on a substrate support in an interior of a plasma etcher, supplying process gas to the interior of the plasma etcher, energizing the process gas into a plasma state, etching the tungsten film by exposing the substrate to the plasma, and heating the substrate to a temperature of at least 100° C. during the etching step. The etching step can include a low temperature main etch below 100° C. followed by a high temperature overetch above 100° C., the process gas including a fluorine containing gas during the main etch and a chlorine containing gas during the overetch. The tungsten film can be located over a dielectric film which serves as a stop layer during the etching step. The tungsten film can be pure tungsten and the dielectric layer can be a silicon oxide film having a thickness of 200 Å or less.

Abstract: A method for fabricating a semiconductor device including a semiconductor layer structure, a source electrode and, a drain electrode formed on the semiconductor layer structure, and a source interconnection connected to the source electrode is provided. The method includes the steps of: (a) forming the semiconductor layer structure on a substrate; (b) forming a metal layer structure so as to cover the semiconductor layer structure; (c) forming a resist layer having a predetermined pattern on the metal layer structure: (d) performing a first etching process for the metal layer structure using the resist layer as a mask so as to form the source electrode, the drain electrode and the source interconnection; and (e) performing a second etching process for the semiconductor layer structure using the resist layer as a mask so as to form a transistor gap portion between the source electrode and the drain electrode.

Abstract: A method of removing remaining photoresist over an Al or Al alloy structure after etching the Al or Al alloy structure in chlorine based plasma, the Al or Al alloy structure being over a substrate, comprises the following steps. The photoresist, Al or Al alloy structure, and the substrate are treated in-situ with organic solvent vapors (such as acetone or carbon tetrachloride) in the absence of plasma excitation at a first predetermined temperature and pressure. The remaining photoresist is then removed with a plasma activated oxygen flow at a second predetermined temperature and pressure.

Abstract: A method of etching silicon oxide with high selectivity to a photoresist mask and to a silicon-containing substrate comprising exposing the silicon oxide to a plasma of a precursor etch gas of a fluorocarbon and an organic silane containing at least one organic group. When at least about 10% by weight of the silane is present in the etch gas, the selectivity between the silicon oxide and the photoresist mask layer, and between the silicon oxide and the silicon-containing substrate, increases markedly. High aspect ratio, submicron size openings can be etched.

Abstract: A self-aligned silicide process with a selective etch of unreacted metal (plus any nitride) with respect to silicide plus a two step process of highly selective strip of unreacted metal (plus any nitride) followed by a silicide etch to remove unwanted silicide filament.

Abstract: A CMP slurry includes a first emulsion having a continuous aqueous phase and a second emulsion. The first emulsion includes abrasive particles, and the second emulsion captures metal particles polished from the semiconductor wafer. Thus, metal particles can be removed from the slurry during CMP to avoid damaging and/or contaminating the semiconductor wafer.

Abstract: The present invention provides a method for forming metal wiring in a semiconductor device, which can improve a reliability of multilayered metal wiring. The process includes forming a first insulating structure on a semiconductor substrate, etching the first insulating film to form a first contact hole, forming a first plug in the first contact hole, and removing a portion of the first insulating structure to planarize the first plug and the remaining portion of the first insulating structure. A first wiring layer is formed on a portion of the first insulating film on and around the first plug. A second insulating structure is deposited on the first wiring layer and the first insulating structure and the second insulating structure is etched to create a via hole which exposes the first wiring layer. A second plug is created in the second contact hole and a portion of the second insulating film is removed to planarize the second plug and the remaining portion of the second insulating structure.

Abstract: The present invention provides fluid compositions for use in the planarization of a substrate surface. Fluid compositions include a planarization slurry having an abrasive component and a chemically interactive component and an effective amount of at least one crown ether that is capable of isolating at least one charged ion contaminant specie in the planarization slurry. Also included are fluid compositions that are pre-treated with an effective amount of at least one crown ether to remove one or more charged ion contaminants in the fluid composition utilized in a planarization process. Methods of using the fluid compositions are also provided.