Abstract: A new method is provided to treat contact holes after hole formation has been completed. A layer of non-conformal dielectric is deposited over the surface in which the contact hole has been formed thereby including the sidewalls and bottom of the contact hole. The non-conformal dielectric will be unevenly deposited on The sidewalls and bottom of the contact hole. This results in a relatively light deposition of non-conformal dielectric along the lower portions of the sidewalls and on the bottom of the contact hole with a heavier coating of non-conformal dielectric being deposited along the upper reaches of the contact hole. The objective of the invention is to prevent the enlargement of the hole diameter during subsequent processing steps. The non-conformal dielectric can be removed from the bottom using a wet etch.

Abstract: A method and apparatus for preparing molten silicon melt from polycrystalline silicon in a crystal pulling apparatus entails loading an amount of polycrystalline silicon loaded into the crucible less than a predetermined total amount of polycrystalline silicon to be melted. The crucible is heated to form a partially melted charge in the crucible having an island of unmelted polycrystalline silicon exposed above an upper surface of melted silicon. Granular polycrystalline silicon is fed from a feeder onto the island of unmelted polycrystalline silicon until the predetermined total amount of polycrystalline silicon has been loaded into the crucible. The position of the island relative to the crucible side wall is electronically determined as granular polycrystalline silicon is fed onto the island.

Abstract: A method and apparatus for monitoring process state using plasma attributes are provided. Electromagnetic emissions generated by a plasma are collected, and a detection signal having at least one frequency component is generated based on the intensity of the collected electromagnetic emissions; or, the RF power delivered to a wafer pedestal is monitored and serves as the detection signal. The magnitude of at least one frequency component of the detection signal then is monitored over time. By monitoring the magnitude of at least one frequency component of the detection signal over time, a characteristic fingerprint of the plasma process is obtained. Features within the characteristic fingerprint provide process state information, process event information and process chamber information. In general, any chemical reaction having an attribute that varies with reaction rate may be similarly monitored.

Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

Abstract: A carbon film is formed over an insulating film and a contact hole is defined therein by patterning. Copper is formed over an entire surface including the contact hole and polished by chemical mechanical polishing. The polishing of the copper is terminated with the carbon film as an etching stopper thereby to allow the copper to remain in the contact hole alone, whereby an embedded interconnection made up of the copper is formed by a damascene method.

Abstract: A method for fabricating a wiring plane with antifuses is described. During the fabrication of the wiring plane on a semiconductor chip with the antifuses, provision is made of a buried antireflection layer in a dielectric layer. In the dielectric layer contact holes are formed, as a result of which only one etching step has to be carried out for the photolithography for forming interconnect trenches above the contact holes.

Abstract: A method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer is disclosed. The method includes depositing a glue layer of TiN followed by tungsten chemical vapor deposition after the contact or via is defined in the dielectric. Then, tungsten etchback or Chemical Mechanical Polishing (CMP) is performed to remove the tungsten and TiN over the dielectric surface with slight dishing of the tungsten within the plug. Next, a blanket deposition of Copper by electrochemical deposition is performed and Copper CMP is used to remove the copper from the dielectric surface while maintaining a coating of copper over the tungsten in the plug. Then, metal stack deposition, patterning and metal etching is performed and a barrier layer of silicon nitride is presented to minimize the copper diffusion. Finally, a deposition of an Interlevel Dielectric (ILD) is deposited.

Abstract: A method for reclaiming a wafer substrate material having a metallic film and a dielectric film includes a step for removing the entire metallic film and a part of the dielectric film with a chemical etching agent so as not to substantially dissolve the wafer substrate material itself, a step for removing the residual dielectric layer and the degenerated zone beneath the surface of the substrate by chemical-mechanical polishing, and a step for polishing at least one surface of the substrate.

Abstract: A baffle plate of a showerhead gas distribution system and method of using the baffle plate wherein the baffle plate is effective for reducing particle and/or metal contamination during processing of semiconductor substrates such as silicon wafers. The showerhead can be a showerhead electrode of a plasma processing chamber such as an etch reactor. The baffle plate comprises silicon on at least one surface thereof and is adapted to fit in a baffle chamber of the gas distribution system such that the silicon containing surface is adjacent to and faces the showerhead. The silicon containing baffle plate can consist entirely of silicon or silicon carbide of at least 99.999% purity. The silicon can be single crystal silicon or polycrystalline and the silicon carbide can be CVD silicon carbide, sintered silicon carbide, non-sintered silicon carbide or combination thereof. The non-sintered silicon carbide can be silicon carbide formed by reaction synthesis of silicon vapor with a carbon material such as graphite.

Abstract: Thinner compositions for effectively removing photoresist. The thinner compositions may be used in reworking a semiconductor substrate or in rinsing semiconductor devices. The thinner composition may be a mixture of n-butyl acetate (n-BA) and ethyl acetate (EA), a mixture of n-butyl acetate (n-BA) and methyl methoxy propionate (MMP), or a mixture of n-butyl acetate (n-BA) and methyl ethyl ketone (MEK).

Abstract: An oxide etch process practiced in magnetically enhanced reactive ion etch (MERIE) plasma reactor. The etching gas includes approximately equal amounts of a hydrogen-free fluorocarbon, most preferably C4F6, and oxygen and a much larger amount of argon diluent gas. The magnetic field is preferably maintained above about 50 gauss and the pressure at 40 milliTorr or above with chamber residence times of less than 70 milliseconds. A two-step process may be used for etching holes with very high aspect ratios. In the second step, the magnetic filed and the oxygen flow are reduced. Other fluorocarbons may be substituted which have F/C ratios of less than 2 and more preferably no more than 1.6 or 1.5.

Abstract: The present invention provides an aqueous dispersion composition for chemical mechanical polishing which is useful for the manufacture of semiconductor devices, and which for polishing of different types of working films and barrier metal layers formed on semiconductor substrates, can achieve efficient polishing particularly of barrier metal surfaces and can give adequately flattened and high precision finished surfaces. The aqueous dispersion composition for chemical mechanical polishing has properties such that, when polishing a copper film, a tantalum layer and/or tantalum nitride layer a and an insulating film under the same conditions, the ratio (RCu/RTa) between the polishing rate of the copper film (RCu) and the polishing rate of the tantalum layer and/or tantalum nitride layer (RTa) is no greater than 1/20, and the ratio (RCu/RIn) between the polishing rate of the copper film (RCu) and the polishing rate of the insulating film (RIn) is from 5 to ⅕.

Abstract: Oxidizing agents are added to slurries of inorganic oxides which have been heated, e.g., autoclaved, to produce abrasive slurries which impart relatively equal polishing rates for conductive metal and insulating layers used to make semiconductor chips. A relatively flexible abrasive slurry in terms of its abrasivity is also provided by this slurry, thereby permitting the modification of a copper polishing slurry's abrasivity when a new insulating material is used to make a chip. When using this method, an increase in particle abrasivity of this slurry can be correlated with a decrease in particle surface area as determined by N2 adsorption (BET method) and abrasivity can be increased (or decreased) by heating the slurry to produce particles with a surface area determined to have the abrasivity desired.

Abstract: A method for producing a single-crystalline film made of a single crystal of lithium potassium niobate-lithium potassium tantalate solid solution or a single crystal of lithium potassium niobate, including the steps of preparing a target made of a material for the single-crystalline film, preparing a foundation made of a single crystal of lithium potassium niobate-lithium potassium tantalate solid solution or a single crystal of lithium potassium niobate, irradiating the target to gasify molecules constituting the target by dissociation and evaporation thereof, and epitaxially growing the single-crystalline film on the foundation.

Abstract: An embodiment of the instant invention is a method of fabricating an electrical device having a structure overlying a semiconductor substrate which is planarized using chemical mechanical planarization, the method comprising the steps of: forming a layer of material over the semiconductor wafer; polishing the layer of material by subjecting it to a polishing pad and a slurry which includes peroxygen; and wherein the slurry additionally includes a stabilizing agent which retards the decomposition of the peroxygen in the slurry. Preferably, the stabilizing agent is comprised of: pyrophosphoric acids, polyphosphonic acids, polyphosphoric acids, Ethylenediamine Tetraacetic acid, a salt of the pyrophosphoric acids, a salt of the polyphosphonic acids, a salt of the polyphosphoric acids, a salt of the Ethylenediamine Tetraacetic acid and any combination thereof. In addition, the stabilizing agent may be comprised of: sodium pyrophosphate decahydrate, sodium pyrophosphate decahydrate, and/or 8-hydroxyquinoline.

Abstract: Rough, conductive diamond film regions are formed on a substrate for establishing electrical contact with a surface mount semiconductor package, or the like. The substrate base is heated in a diamond film gas phase deposition reactor. Molecular hydrogen, a carbon-bearing gas and a dopant source are introduced into the reactor at a temperature conducive to producing a conductive polycrystalline diamond film with sharp facets extending from the film. The diamond film is patterned by etching to remove regions where no electrical contact with the surface mount package is desired.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: A method for determining the AB etch endpoint during an silicon trench isolation fabrication process requires the introduction into the STI design a sufficient quantity of “dummy” diffusion structures that provide a strong endpoint signal during normal STI fabrication and, that which endpoint signal may be controlled by adjustment of the planarization shapes associated with the dummy diffusion structures.

Abstract: A method for forming a patterned composite stack layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket first silicon layer. There is then formed forming upon the blanket first silicon layer a blanket silicon containing dielectric layer. There is then formed upon the blanket silicon containing dielectric layer a blanket second silicon layer. There is then formed upon the blanket second silicon layer a blanket organic polymer anti-reflective coating (ARC) layer. There is then formed upon the blanket organic polymer anti-reflective coating (ARC) layer a patterned photoresist layer.

Abstract: Within a method for forming a plasma etched layer, there is first provided a substrate. There is then formed over the substrate a microelectronic layer. There is then etched within a plasma reactor chamber, and while employing a plasma etch method, the microelectronic layer to form a plasma etched microelectronic layer. Finally, there is then purged the plasma reactor chamber with an inert purge gas, without subsequently evacuating the plasma reactor chamber, prior to removing the substrate having formed thereover the plasma etched microelectronic layer from the plasma reactor chamber. In an alternative there is purged a load lock chamber integral to the plasma reactor chamber with an inert purge gas, without subsequently evacuating the load lock chamber, prior to removing the substrate having formed thereover the plasma etched microelectronic layer from the load lock chamber.