Patents Examined by Benjamin Sandvik
  • Patent number: 10239158
    Abstract: Laser hybrid welding systems adapted to identify and/or fix a weld defect occurring during a laser hybrid welding process are provided. Embodiments of the laser hybrid welding system may include one or more devices that provide feedback to a controller regarding one or more weld parameters. One embodiment of the laser hybrid welding system includes sensors that are adapted to measure the weld voltage and/or amperage during the welding process and transmit the acquired data to the controller for processing. Another embodiment of the laser hybrid welding system includes a lead camera and a lag camera that film an area directly in front of the weld location and directly behind the weld location.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 26, 2019
    Assignee: Illinois Tool Works Inc.
    Inventor: Bruce Patrick Albrecht
  • Patent number: 10229365
    Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 12, 2019
    Assignees: NewSouth Innovations Pty Limited, University of Melbourne
    Inventors: Martin Fuechsle, Samuel James Hile, Charles David Hill, Lloyd Christopher Leonard Hollenberg, Matthew Gregory House, Eldad Peretz, Sven Rogge, Michelle Yvonne Simmons
  • Patent number: 10224408
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10217706
    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Kyle Armstrong, Michael D. Hyatt, Michael Dean Van Patten, David A. Kewley, Ming-Chuan Yang
  • Patent number: 10209695
    Abstract: In aspects, the present invention discloses a method for replacing a first field device with a second field device using a commissioning tool. The method comprising retrieving a device description file associated with the first field device, analyzing the device description file, generating a first object by mapping a parameters of the second field device to a parameter from the identified one or more parameters based on a first index and a second index, generating a configuration file associated with the second file device based on the device description file and the generated first object, and transmitting the configuration file to the second field device for commissioning operation of the second field device. The step of analyzing the device description file comprises identifying one or more parameters from the plurality of parameters for mapping based on a predetermined criteria.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: February 19, 2019
    Assignee: ABB Schweiz AG
    Inventors: Ravish Kumar, Deepaknath Tandur, Mallikarjun Kande, Roland Braun, Bhangale Milind, Neil Shah, Stefan Bollmeyer, Shashishekhar Pandharkar
  • Patent number: 10195682
    Abstract: A system and method for cutting a workpiece utilizing a plasma cutting tool of fixed cut width into at least two parts having prescribed shapes from a metal plate comprising the steps of: identifying each of the parts by one or more contour lines; cutting a workpiece along one of the identifying contour lines into one of the parts using a tool of fixed cutting width; utilizing this cut contour of fixed width as part of the contour on an adjacent part fully overlapping the cut width. The process is repeated until all the required parts are cut.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 5, 2019
    Inventor: Matthew Fagan
  • Patent number: 10192982
    Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 29, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
  • Patent number: 10185192
    Abstract: The present disclosure discloses a Thin Film Transistor array substrate, a method for manufacturing the same and a method for maintaining the same, and a display panel. The TFT array substrate includes: a substrate; gate lines, common electrode lines and data lines arranged on the substrate; and pixel electrodes arranged at pixel unit regions defined by the gate lines and the data lines. The TFT array substrate further includes weld metal electrically connected to the pixel electrodes. Projections of the weld metal onto the substrate and projections of target wires onto the substrate are overlapped at overlapping regions, and the target wires are the gate lines or the common electrode lines.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: January 22, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xingfeng Ren, Chong Fang
  • Patent number: 10185046
    Abstract: Method for correcting seismic simulations, RTM, and FWI for temporal dispersion due to temporal finite difference methods in which time derivatives are approximated to a specified order of approximation. Computer-simulated seismic data (51) are transformed from time domain to frequency domain (52), and then resampled using a mapping relationship that maps, in the frequency domain, to a frequency at which the time derivative exhibits no temporal dispersion (53), or to a frequency at which the time derivative exhibits a specified different order of temporal dispersion. Alternatively, measured seismic data from a field survey (61) may have temporal dispersion of a given order introduced, by a similar technique, to match the order of approximation used to generate simulated data which are to be compared to the measured data.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: January 22, 2019
    Assignee: ExxonMobil Upstream Research Company
    Inventors: John E. Anderson, Anatoly Baumstein, Carey Marcinkovich, Tetyana Vdovina, Valeriy Brytik
  • Patent number: 10181440
    Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yukio Takahashi, Hitoshi Matsuura
  • Patent number: 10172558
    Abstract: A high aspect ratio shadow mask and a method of making and using the high aspect ratio shadow mask can provide multiple conductive trace pathways along high aspect ratio electrodes. The high aspect ratio shadow mask can include a substantially planar base layer and a plurality of hollow high aspect ratio projections extending from the substantially planar base layer. The high aspect ratio shadow mask can further include a plurality of openings along the hollow projections which define trace deposition patterns.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 8, 2019
    Assignee: University of Utah Research Foundation
    Inventors: Sandeep Negi, Rajmohan Bhandari, Mobashir Hasan Shandi
  • Patent number: 10177166
    Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyun Kang, Hyun Lee, Min-Su Kim, Ji-Kyum Kim, Jong-Woo Kim
  • Patent number: 10170681
    Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be annealed with a thermal source. The thermal source may be a laser that generates a Gaussian beam. An axicon lens may be exposed to the Gaussian beam. Annealing the Josephson junction may alter the resistance of the Josephson junction.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Jason S. Orcutt
  • Patent number: 10168302
    Abstract: Embodiments relate to a signal processing system and method in particular for determining the location of a feature within a hollow body using deconvolution of measured acoustic waves.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: January 1, 2019
    Assignee: The University of Manchester
    Inventors: Barry Lennox, Keir Groves
  • Patent number: 10166615
    Abstract: A machine including: a table having a surface adapted to have a workpiece lay and move thereon, and a vise for gripping the workpiece. The machine also includes a drive system for moving the vise and workpiece a distance along the table surface, and a sensor assembly connected to the vise for measuring an amount of slip distance occurring between the vise and the workpiece. The machine also includes a control unit connected to the sensor assembly and the drive system for storing the measured slip distance and for operating the drive system and for operating to do at least one of, when a predetermined amount of slip distance is detected: sounding an alarm and stopping further movement of the workpiece, and, when a slip distance is measured, for causing the drive system to move the vise and workpiece an added distance equal to the measured slip distance.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 1, 2019
    Assignee: Marvel Manufacturing Company, Inc.
    Inventors: James Jourdan, Dean T Saari, Marti Kallas
  • Patent number: 10164007
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10163912
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Patent number: 10163727
    Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jelin Wang, Ching-Chen Hao, Yi-Huang Wu, Meng Yi Sun
  • Patent number: 10158065
    Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: December 18, 2018
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Doyle, Kaan Oguz, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, David L. Kencke, Robert S. Chau, Roksana Golizadeh Mojarad
  • Patent number: 10151806
    Abstract: A method and an apparatus are for the permanent magnetization of at least one ferromagnetic layer in a magnetic field sensor device deposited on a chip substrate. The method includes production of at least one resistance element on a chip substrate, deposition of at least one soft magnetic structuring element on the chip substrate; heating of the resistance element to above the blocking temperature and coupling of a preconditioning magnetic field; cooling of the resistance element to below the blocking temperature; and removal of the preconditioning magnetic field. The soft magnetic structuring element is arranged such that the coupled preconditioning magnetic field penetrates the structuring element substantially perpendicular to the chip surface and, at the location of the resistance element, generates magnetic field components parallel to the chip surface which penetrate the ferromagnetic layer of the resistance element at least in some areas.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 11, 2018
    Assignee: SENSITEC GMBH
    Inventors: Jochen Schmitt, Johannes Paul, Ronald Lehndorff, J├╝rgen Wahrhusen, Claudia Glenske