Patents Examined by Benjamin Sandvik
  • Patent number: 10002884
    Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Ryota Hodo, Shinya Sasagawa, Yuki Hata
  • Patent number: 10002971
    Abstract: A change in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor having an oxide semiconductor. A semiconductor device includes a transistor, and the transistor includes an oxide semiconductor film over a first insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a conductive film in contact with a side surface of the gate electrode in a channel length direction, and a second insulating film over the oxide semiconductor film. The oxide semiconductor film includes a first region overlapping with the gate electrode, a second region overlapping with the conductive film, and a third region in contact with the second insulating film. The third region includes a region having higher impurity element concentration than the second region.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Takahiro Iguchi
  • Patent number: 10002897
    Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 19, 2018
    Assignee: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano
  • Patent number: 10002952
    Abstract: A silicon carbide (SiC) semiconductor device, including a SiC substrate, a first SiC layer formed on the substrate, first and second impurity layers selectively formed in the first SiC layer, a second SiC layer formed on the first SiC layer, a third impurity layer selectively formed in the second SiC layer and on the second impurity layer, a third SiC layer formed on the second SiC layer, a fourth impurity layer selectively formed in the third SiC layer, a trench that penetrates the fourth impurity layer and the second and third SiC layers, a bottom thereof reaching the first impurity layer, and a gate electrode formed in the trench via a gate insulating film. The first SiC layer has first and second regions adjacent respectively to the first and second impurity layers on a side facing the substrate, an impurity concentration at the first region being lower than that at the second region.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 19, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiyuki Sugahara, Keiji Okumura
  • Patent number: 9997683
    Abstract: A light emitting device package is provided. The light emitting device package may include a frame, a first lead frame spaced apart from the frame, a second lead frame spaced apart from the frame, a body coupled to the frame and the first and second lead frames and having a first cavity, and a plurality of light emitting devices on the frame exposed through the first cavity. The body may include a reflective part provided inside the first cavity to surround at least one of the light emitting devices, thereby improving light extraction efficiency.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 12, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chung Hee Ryu, Bong Kul Min, Won Jin Son, Won Bong Lee
  • Patent number: 9997537
    Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Lee, Jee-Yong Kim, Dae-Seok Byeon
  • Patent number: 9991215
    Abstract: A semiconductor structure includes a substrate including a first side and a second side opposite to the first side; a first via extending through the substrate; a second via extending through the substrate; and a metallic structure disposed between the first via and the second via, wherein the first via is isolated from the second via by the metallic structure, the first via and the second via are configured to connect to a signal source or transmit a signal, and the metallic structure is configured to connect to a power or a ground.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 5, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 9985121
    Abstract: A FET device includes a substrate having top and bottom surfaces, a channel layer on the top surface of the substrate; the channel layer having top and bottom surfaces, at least two recesses extending into the channel layer from the top surface of the channel layer and forming a channel region between the at least two recesses, a gate electrode disposed in each of the at least two recesses, and a drain region and a source region formed in the channel layer on opposite sides of said channel region.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: May 29, 2018
    Assignee: HRL Laboratories, LLC
    Inventor: Kenneth R. Elliott
  • Patent number: 9984934
    Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Maekawa, Tatsuyoshi Mihara
  • Patent number: 9984888
    Abstract: A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 29, 2018
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Hadi Jebory
  • Patent number: 9985089
    Abstract: Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 9985061
    Abstract: A light detection device includes: a TFT having a semiconductor layer supported on a substrate, a source electrode, a drain electrode, and a gate electrode; a photodiode having a bottom electrode electrically connected to the drain electrode, a semiconductor laminate structure, and a top electrode; and an electrode made of the same conductive film as the bottom electrode and arranged on the semiconductor layer with an insulating layer interposed therebetween.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 29, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Kazuhide Tomiyasu, Atsushi Tomyo, Kazuatsu Ito, Shigeyasu Mori
  • Patent number: 9977301
    Abstract: The present invention discloses an array substrate, comprising a first storage capacitor and a second storage capacitor, and the first storage capacitor and the second storage capacitor are coupled in parallel to form a total storage capacitor of the array substrate to increase the total storage capacitor of the array substrate, so as to avoid the issues of the cross talk and the image residue due to the over small total storage capacitor for promoting the quality of the array substrate. The present invention further discloses a display panel utilizing the array substrate and a liquid crystal display panel utilizing the array substrate.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 22, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yuanfu Liu
  • Patent number: 9978864
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 22, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tse-Hsiao Liu, Sing-Lin Wu, Chung-Hsuan Wang, Yung-Lung Chou, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 9978865
    Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hong Kwon, Youngho Lee, Hoon Lim, Hyungsoon Jang, Eunguk Chung
  • Patent number: 9971329
    Abstract: A cell control system including a communication device for communicating with a manufacturing cell including a plurality of manufacturing machines configured to manufacture a product, an obtaining module for obtaining first manufacturing information in a manufacturing cell unit associated with the manufacture of the product, a first generation module for generating a plurality of pieces of second manufacturing information for the plurality of manufacturing machines, based on the first manufacturing information, a transmission module for transmitting the plurality of pieces of second manufacturing information to the plurality of manufacturing machines, a reception module for receiving manufacturing machine-specific, third manufacturing information corresponding to the second manufacturing information from the plurality of manufacturing machines, a second generation module for generating fourth manufacturing information in the manufacturing cell unit, based on the third manufacturing information from the plural
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 15, 2018
    Assignee: FANUC CORPORATION
    Inventors: Shinsuke Sakakibara, Hiroji Nishi
  • Patent number: 9972488
    Abstract: A method of reducing defects in an epitaxial layer. The method includes forming one or more barrier structures within a peripheral edge region of a wafer substrate, and forming an epitaxial layer over a surface of the wafer substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Helmut Oefner, Johannes Baumgartl
  • Patent number: 9972748
    Abstract: A method for producing a thin-film semiconductor body is provided. A growth substrate is provided. A semiconductor layer with funnel-shaped and/or inverted pyramid-shaped recesses is epitaxially grown onto the growth substrate. The recesses are filled with a semiconductor material in such a way that pyramid-shaped outcoupling structures arise. A semiconductor layer sequence with an active layer is applied on the outcoupled structures. The active layer is suitable for generating electromagnetic radiation. A carrier is applied onto the semiconductor layer sequence. At least the semiconductor layer with the funnel-shaped and/or inverted pyramid-shaped recesses is detached, such that the pyramid-shaped outcoupling structures are configured as projections on a radiation exit face of the thin-film semiconductor.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 15, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Christian Leirer, Anton Vogl, Andreas Biebersdorf, Rainer Butendeich, Christian Rumbolz
  • Patent number: 9966496
    Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 8, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9966497
    Abstract: A method of fabricating a nonpolar gallium nitride-based semiconductor layer is provided. The method is a method of fabricating a nonpolar gallium nitride layer using metal organic chemical vapor deposition, and includes disposing a gallium nitride substrate with an m-plane growth surface within a chamber, raising a substrate temperature to a GaN growth temperature by heating the substrate, and growing a gallium nitride layer on the gallium nitride substrate by supplying a Ga source gas, an N source gas, and an ambient gas into the chamber at the growth temperature. The supplied ambient gas contains N2 and does not contain H2.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: May 8, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seung Kyu Choi, Chae Hon Kim, Jung Whan Jung