Patents Examined by Benjamin Sandvik
  • Patent number: 10038067
    Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Bahman Hekmatshoartabari
  • Patent number: 10037886
    Abstract: A method of manufacturing a silicon carbide semiconductor device having a contact formed between a p-type silicon carbide semiconductor body and a metal electrode, includes forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce a potential difference generated in a conjunction interface between the p-type silicon carbide semiconductor body and the metal electrode; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming the metal electrode on a surface of the insulation layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 31, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Fujii, Mariko Sato, Takuro Inamoto
  • Patent number: 10037885
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10033015
    Abstract: For a flexible, optically clear display stack, an adhesive, a system, and a method are provided. The adhesive is formed of polymer chains, at least a portion of which are cross-linked, a non-volatile diluent having a volume % in the range of between about 40 and 95, and is characterized with a low shear modulus of less than 10 kPa. The system is formed by at least first and second optically clear thin films with the adhesive disposed between the first and second thin films. The method includes the steps to form the system.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 24, 2018
    Assignee: Motorola Mobility LLC
    Inventors: Richard Brotzman, Deborah M. Paskiewicz
  • Patent number: 10032791
    Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
  • Patent number: 10026736
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 10026913
    Abstract: A quantum dot electronic device comprises a first encapsulation layer, a first electrode disposed on the first encapsulation layer, a quantum dot pattern disposed on the first electrode, a second electrode disposed on the quantum dot pattern and a second encapsulation layer disposed on the second electrode. The quantum dot pattern may be formed by an intaglio transfer printing method, where the method comprises forming a quantum dot layer on a donor substrate, picking up the quantum dot layer using a stamp, putting the quantum dot layer into contact with an intaglio substrate using the stamp and separating the stamp from the intaglio substrate. Using the quantum dot transfer printing method, a subminiature quantum dot pattern can be transferred at a high transfer rate. Accordingly, a highly integrated quantum dot electronic device exhibiting excellent performance and a high integrated quantum dot light emitting device with an ultrathin film can be realized.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: July 17, 2018
    Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, INSTITUTE FOR BASIC SCIENCE
    Inventors: Daehyeong Kim, Taeghwan Hyeon, Moonkee Choi, Jiwoong Yang, Kwanghun Kang
  • Patent number: 10020336
    Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Naoto Kusumoto
  • Patent number: 10020399
    Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: July 10, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshiharu Nagumo
  • Patent number: 10018465
    Abstract: An inspection system, in an embodiment, can be operable with a probe and a position tracker to inspect an object. The system can be operable to display at least one probe travel axis, receive first and second inspection values from the probe, associate the first inspection value with a first position point, and associate the second inspection value with a second position point. The system displays an inspection path based on the associations. The inspection path extends relative to the probe travel axis.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 10, 2018
    Inventor: Daniel Scott Groninger
  • Patent number: 10014397
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, David L. Harame, Renata Camillo-Castillo
  • Patent number: 10012855
    Abstract: A display device includes a pixel substrate in which a plurality of wirings and a plurality of switching elements are formed. The pixel substrate includes an organic insulating film formed over the substrate, a first wiring and a second wiring arranged in parallel on the organic insulating film, a trench formed in the organic insulating film between the first wiring and the second wiring, and a protection film formed to cover the first wiring, the second wiring, and the trench.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 3, 2018
    Assignee: Japan Display Inc.
    Inventor: Hideki Shiina
  • Patent number: 10014376
    Abstract: A silicon carbide semiconductor device includes: a silicon carbide off substrate including a main surface having an off angle relative to a basal plane, the main surface being provided with a trench, the trench having a plurality of side walls and a bottom portion; a gate insulating film covering the side walls and the bottom portion; and a gate electrode provided on the gate insulating film, each of the side walls having an angle of more than 65° and not more than 80° relative to the basal plane in the trench, opening directions of the plurality of side walls being all at a silicon plane side or a carbon plane side.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 3, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Hideto Tamaso
  • Patent number: 10014488
    Abstract: An optoelectronic component may include a carrier, above which a first electrode is formed. An optically functional layer structure is formed above the first electrode. A second electrode is formed above the optically functional layer structure, the second electrode extending areally over at least one part of the side of the optically functional layer structure which faces away from the carrier. An encapsulation is formed above the first and/or second electrode, the encapsulation encapsulating the optically functional layer structure. An electrically conductive contact structure is arranged in a cutout of the encapsulation on the first and/or second electrode and extends through the encapsulation, for electrically contacting the first and/or second electrode. The contact structure and the encapsulation are formed such that in interaction they encapsulate the first and/or second electrode.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: July 3, 2018
    Assignee: OSRAM OLED GmbH
    Inventor: Philipp Schwamb
  • Patent number: 10008581
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10008590
    Abstract: A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 26, 2018
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 10009001
    Abstract: Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the titanium tungsten layer. The photo resist material is exposed under a defocus condition to generate a resist mask, wherein an edge of the exposed photo resist material corresponds to the sloped termination. The titanium tungsten layer is etched with an etching material, wherein the etching material at least partially etches the photo resist material exposed under the defocused condition, and wherein the etching results in the sloped termination in the titanium tungsten layer.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neng Jiang, Maciej Blasiak, Nicholas S. Dellas, Brian E. Goodlin
  • Patent number: 10008636
    Abstract: A light-emitting device is provided. comprises: a light-emitting stack comprising an active layer emitting a first light having a first peak wavelength ? nm; and an adjusting element stacked on and electrically connected to the active layer, wherein the adjusting element comprises a diode emitting a second light having a second peak wavelength between 800 nm and 1900 nm; wherein a forward voltage of the light-emitting device is between (1240/0.8?) volt and (1240/0.5?) volt, and a ratio of the intensity of the first light emitted from the active layer at the first peak wavelength to the intensity of the second light emitted from the diode at the second peak wavelength is greater than 10 and not greater than 1000.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 26, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Chiang Lu, Yi-Chieh Lin, Rong-Ren Lee, Yu-Ren Peng, Ming-Siang Huang, Ming-Ta Chin, Yi-Ching Lee
  • Patent number: 10008651
    Abstract: A first conductive pattern is disposed on a substrate. A first conductive pattern includes a first element mount portion and a first wire connection portion. A second conductive pattern is disposed on the substrate to be spaced apart from the first conductive pattern. The second conductive pattern includes a second element mount portion and a groove. The second element mount portion has a first side, a second side substantially orthogonal to the first side, and a third side substantially orthogonal to the first side and substantially parallel to the second side. The groove extends substantially parallel to the first side. A rectangular first light emitting element is disposed on the first element mount portion. A rectangular second light emitting element is disposed on the second element mount portion adjacent to the first light emitting element. A wire connects the second light emitting element to the first wire connection portion.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 26, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Masato Ono
  • Patent number: 10008499
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi