Patents Examined by Benjamin Sandvik
  • Patent number: 10090320
    Abstract: A semiconductor device according to an embodiment, includes a stacked body, a plurality of first terraces, a second terrace, a plurality of interconnects, a plurality of conductive bodies. The stacked body includes a plurality of electrode layers. The stacked body includes a stairstep portion at an end portion of the stacked body. The plurality of first terraces are provided in the stairstep portion. The second terrace is provided in the stairstep portion. The plurality of interconnects are provided from the second terrace to the plurality of first terraces. The plurality of interconnects contact one of the plurality of electrode layers at the stairstep portion. The plurality of conductive bodies are provided above the second terrace. The plurality of conductive bodies extend in a stacking direction of the stacked body. The conductive bodies contact the interconnects above the second terrace.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 2, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Nogami, Gaku Sudo
  • Patent number: 10083880
    Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
  • Patent number: 10084134
    Abstract: In a method for stretching a vapor deposition mask including a metal mask in which a slit is formed and a resin mask in which an opening corresponding to a pattern to be produced by vapor deposition is formed at a position overlapping with the slit, a stretching assistance member is overlapped on one surface of the vapor deposition mask, the stretching assistance member is fixed to the vapor deposition mask in at least part of a portion in which the one surface of the vapor deposition mask and the stretching assistance member overlap with each other, and the vapor deposition mask fixed to the stretching assistance member is stretched by pulling the stretching assistance member fixed to the vapor deposition mask.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 25, 2018
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Hideyuki Okamoto, Yoshiyuki Honma, Toshihiko Takeda
  • Patent number: 10083927
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10079312
    Abstract: A metal element of a metal film is introduced into the oxide semiconductor film by performing heat treatment in the state where the oxide semiconductor film is in contact with the metal film, so that a low-resistance region having resistance lower than that of a channel formation region is formed. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. After that, an unnecessary metal film is removed. Thus, the metal oxide insulating film can be formed over the low-resistance region.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 18, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Kosei Noda, Yoshiaki Oikawa
  • Patent number: 10079303
    Abstract: A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10073447
    Abstract: In industrial machine abnormality diagnosis, if the machine is diagnosed to have abnormality, then sensor data from the machine needs to be sent to a management center for causal analysis. However, since machines operated at a remote site cannot always communicate with a management center, it has been found that, in some cases, sensor data that has failed to be sent from a machine remains in the memory of the machine, resulting in lack of available memory capacity. In view of this, the present invention determines beforehand whether the diagnosed machine will run out of available memory capacity before the completion of sending the amount of sensor data required for causal analysis for the machine, and instructs a maintenance person to recover memory.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 11, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uchida, Hideaki Suzuki, Junsuke Fujiwara, Tomoaki Hiruta, Munetoshi Unuma
  • Patent number: 10074736
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 10069010
    Abstract: A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshiharu Nagumo
  • Patent number: 10068906
    Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 10062814
    Abstract: A method of manufacturing a light emitting device, includes: temporarily connecting light emitting elements to a wiring layer through connection members, the wiring layer being formed on a mounting board provided with reflectors; contacting a pressing surface of a press-bonding jig with upper surfaces of the light emitting elements and pressing the light emitting elements toward the mounting board while being heated at the same time to deform the connection members and to contact the pressing surface with tops of the reflectors; and connecting the light emitting elements to the wiring layer in a flip chip manner, wherein when the light emitting elements are temporarily connected to the wiring layer, a sum of height of a light emitting element of the light emitting elements and a connection member of the connection members is set to be larger than a height of a reflector of the reflectors.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 28, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yosuke Tsuchiya, Yuhki Ito, Aya Kawaoka
  • Patent number: 10056424
    Abstract: A semiconductor device includes an SOI substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and an interlayer insulation film formed on the SOI substrate. The SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region. The circuit layer includes a plurality of single pixel circuits arranged in an array pattern. The single pixel circuit includes a circuit element, a diode, and a conductive portion. The diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region. The conductive portion is electrically isolated from other elements. The conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 21, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroki Kasai
  • Patent number: 10056396
    Abstract: A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a floating gate is removed by using a spacer insulating film, a first insulating film, and a second insulating film as a mask. A floating gate having a tip portion is formed from the conductive layer for the floating gate, and a part of an insulating layer for a gate insulating film is exposed from the floating gate. The tip portion of the floating gate is further exposed by selectively removing the second insulating film among the second insulating film, the insulating layer for the gate insulating film, and the spacer insulating film.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Mukai
  • Patent number: 10056427
    Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a substrate and a barrier structure formed in the substrate. The barrier structure includes a plurality of protrusion portions and a plurality of pillar portions. Each of the protrusion portions has a first height, and each of the pillar portions has a second height that is greater than the first height. The FSI image sensor device structure includes a pixel region formed over the protrusion portions and a storage region formed over the protrusion portions, wherein the pillar portions surround the pixel region.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Heng Jiang, Ming-Chi Wu, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh
  • Patent number: 10050059
    Abstract: A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively disposed on the gate insulating film; a source electrode and a drain electrode that are spaced from each other on the transparent oxide film; and a light transmissive pixel electrode electrically connected to the drain electrode. The transparent oxide film includes a conductive region and a semiconductor region. The conductive region is disposed in a lower portion of the source electrode and the drain electrode and disposed in a portion that continues from the lower portion of the drain electrode, extends to part of an upper portion of the common electrode, and forms the pixel electrode. The semiconductor region is disposed in a portion corresponding to a lower layer in a region between the source electrode and the drain electrode.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunori Inoue, Koji Oda, Naoki Tsumura
  • Patent number: 10043966
    Abstract: A semiconductor device includes a lower insulating layer on a substrate, a lower wiring layer extending on the lower insulating layer, a lower surface of at least a part of the lower wiring layer being covered by the lower insulating layer, a plurality of via plugs extending in a first direction on the lower wiring layer, the plurality of via plugs including a real via plug and a first dummy via plug connected to the part of the lower wiring layer covered by the lower insulating layer, and an upper wiring layer overlapping the lower wiring layer and extending in a second direction different from the first direction on the real via plug, the upper wiring layer not overlapping the dummy via plug.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hoon Bak, Kyung-tae Nam, Yong-jae Kim, Da-hye Shin
  • Patent number: 10043875
    Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Bahman Hekmatshoartabari
  • Patent number: 10043805
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 7, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10043898
    Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 7, 2018
    Assignee: Transphorm Inc.
    Inventor: Rakesh K. Lal
  • Patent number: 10038121
    Abstract: A light emitting diode including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, and a Bragg reflector structure. The emitting layer is configured to emit a light beam and is located between the first-type semiconductor layer and the second-type semiconductor layer. The light beam has a peak wavelength in a light emitting wavelength range. The first-type semiconductor layer, the emitting layer, and the second-type semiconductor layer are located on a same side of the Bragg reflector structure. A reflectance of the Bragg reflector structure is greater than or equal to 95% in a reflective wavelength range at least covering 0.8X nm to 1.8X nm, and X is the peak wavelength of the light emitting wavelength range.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: July 31, 2018
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting