Patents Examined by Benjamin Sandvik
  • Semiconductor device including a semiconductor sheet interconnecting a source region and a drain region
    Patent number: 9711596
    Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hao-Ling Tang, Jon-Hsu Ho, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai
  • Integrated circuits with optical modulators and photodetectors and methods for producing the same
    Patent number: 9711662
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming an upper interlayer dielectric overlying an optical modulator and a photodetector, where the photodetector has a shoulder and a plug. An etch stop is formed overlying the upper interlayer dielectric. The etch stop is a first, second, and third distance from an uppermost surface of the optical modulator, the shoulder, and the plug, respectively, where the first, second, and third distances are all different from each other. A first, second, and third contact are formed through the upper interlayer dielectric, where the first, second and third contacts are in electrical communication with the optical modulator, the shoulder, and the plug, respectively.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Benfu Lin, Juan Boon Tan, Ramakanth Alapati
  • Method of manufacturing semiconductor device
    Patent number: 9704844
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: July 11, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
  • Method for manufacturing a silicon carbide device and a silicon carbide device
    Patent number: 9704718
    Abstract: A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Ralf Otremba, Jens Konrath
  • Image sensor and method of manufacturing the same
    Patent number: 9704909
    Abstract: An image sensor is provided. The sensor comprises a plurality of photoelectric conversion elements each including a charge accumulation region of a first conductivity type arranged in a semiconductor substrate and an element isolation region arranged between the charge accumulation regions adjacent to each other. The element isolation region includes an insulator isolation portion arranged on an inner side of a trench on a surface of the semiconductor substrate, and includes a semiconductor region of a second conductivity type opposite to the first conductivity type arranged along a side surface of the insulator isolation portion. A gettering region is arranged between the semiconductor region and the insulator isolation portion along at least a part of the side surface of the insulator isolation portion.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: July 11, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tasuku Kaneda
  • Vertical MIM capacitor
    Patent number: 9698213
    Abstract: Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Light emitting device having UV light emitting diode for generating human-friendly light and lighting apparatus including the same
    Patent number: 9698317
    Abstract: The light emitting device includes: an ultraviolet light emitting diode emitting light in an ultraviolet wavelength region; and blue phosphors, green phosphors, and red phosphors excited by the ultraviolet light emitting diode, wherein white light is formed by synthesis of the light emitted from the ultraviolet light emitting diode, light emitted from the blue phosphors, light emitted from the green phosphors, and light emitted from the red phosphors, the white light includes ultraviolet light, green light, blue light, and red light, an intensity of a peak wavelength of the green light is in a range of 1.8 to 2.1 times the intensity of a peak wavelength of the blue light, and an intensity of a peak wavelength of the red light is in a range of 2.8 to 3.1 times the intensity of the peak wavelength of the blue light.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 4, 2017
    Assignee: SEOUL SEMICONDUCTOR CO., LTD.
    Inventors: Sang Shin Park, Kwang Yong Oh, Myung Jin Kim, Ki Bum Nam
  • Semiconductor device
    Patent number: 9698258
    Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: July 4, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Yu Shin Ryu, Tae Hoon Lee, Bo Seok Oh
  • Thin film transistor substrate and display using the same
    Patent number: 9691799
    Abstract: The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same. A display includes a first thin film transistor including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: June 27, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Youngjang Lee, Kyungmo Son, Sohyung Lee, Moonho Park, Sungjin Lee
  • Vertical cross-point arrays for ultra-high-density memory applications
    Patent number: 9691821
    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: June 27, 2017
    Assignee: Unity Semiconductor Corporation
    Inventor: Bruce Lynn Bateman
  • Semiconductor device including transistors and diodes and a first line extending between the transistors and diodes
    Patent number: 9691757
    Abstract: Reduction of the speed of switching between the drain electrodes of transistors and the cathode electrodes of diodes due to the inductances of lines coupling them is inhibited. Transistors and diodes are formed over a substrate. The transistors and the diodes are arranged in a first direction. The substrate also includes a first line, first branch lines, and second branch lines formed thereover. The first line extends between the transistors and the diodes. The first branch lines are formed to branch from the first line in a direction to overlap the transistors and are coupled to the transistors. The second branch lines are formed to branch from the first line in a direction to overlap the diodes and are coupled to the diodes.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: June 27, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshinao Miura
  • Magnetic memory device
    Patent number: 9691457
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive effect element, and a first layer provided on the magnetoresistive effect element, wherein the first layer includes an upper conductive layer, and a predetermined metal containing conductive layer provided between the magnetoresistive effect element and the upper conductive layer and containing a predetermined metal selected from Pt, Ir, Pd and Au.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 27, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshinori Kumura
  • Methods and devices for back end of line via formation
    Patent number: 9691654
    Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sunil Kumar Singh, Sohan Singh Mehta, Ravi Prakash Srivastava
  • SiGe CMOS with tensely strained NFET and compressively strained PFET
    Patent number: 9685510
    Abstract: A method includes providing a Si substrate having an overlying layer of Si1-xGex; growing, over the layer of Si1-xGex, a layer of Si in an NFET region and a second layer of Si1-xGex in a PFET region; partitioning the layer of Si1-xGex into a structure including a first Si1-xGex sub-layer disposed in the NFET region and a second Si1-xGex sub-layer disposed in the PFET region; annealing the structure to convert the first Si1-xGex sub-layer and the overlying Si layer into a tensily strained Si1-xGex intermixed layer and to convert the second Si1-xGex sub-layer and the overlying second layer of Si1-xGex into a compressively strained Si1-xGex intermixed layer, where a value of x in the tensily strained Si1-xGex intermixed layer is less than a value of x in the compressively strained Si1-xGex intermixed layer and forming a first transistor in the NFET region and a second transistor in the PFET region.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Back-illuminated integrated imaging device with simplified interconnect routing
    Patent number: 9685475
    Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 20, 2017
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
  • Array substrate, method for manufacturing the same and liquid crystal display device
    Patent number: 9684217
    Abstract: An array substrate, a method for manufacturing the same and a liquid crystal display device are provided. A metal oxide semiconductor layer and an etching stop layer are sequentially formed on a gate insulating layer. One patterning process is performed in the etching stop layer to form a source electrode contact region via hole, a drain electrode contact region via hole and an insulation region. A source-drain electrode layer is formed on the etching stop layer. During a process of performing one patterning process in the source-drain electrode layer to form a source-drain electrode pattern, a portion of the metal oxide semiconductor layer corresponding to the insulation region is removed so that the metal oxide semiconductor layer is disconnected at a position corresponding to the insulation region. The insulation region surrounds the source-drain electrode pattern.
    Type: Grant
    Filed: January 4, 2015
    Date of Patent: June 20, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiang Liu
  • Semiconductor apparatus including barrier film provided between electrode and protection film
    Patent number: 9685547
    Abstract: A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: June 20, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Ohki
  • Anisotropic conductive adhesive
    Patent number: 9676066
    Abstract: An anisotropic conductive adhesive in which high thermal dissipation is provided. Conductive particles and solder particles are dispersed in a binder. In a thermally compressed LED device manufactured using this anisotropic conductive adhesive, terminals of the LED device are electrically connected to terminals of a substrate via particles and the terminals of the LED device and the terminals of the substrate are solder bonded.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: June 13, 2017
    Assignee: DEXERIALS CORPORATION
    Inventors: Akira Ishigami, Shiyuki Kanisawa, Hidetsugu Namiki, Masaharu Aoki
  • Semiconductor pressure sensor and method of fabricating same
    Patent number: 9676616
    Abstract: In a semiconductor pressure sensor, a fixed electrode is formed as the same layer as a diffusion layer formed to extend from a surface of a semiconductor substrate to inside of the semiconductor substrate. A void is formed by removing a sacrifice film, which is a region constituted of the same film as a floating gate electrode. A movable electrode includes an anchor portion which supports the movable electrode via the void relative to the fixed electrode and in which the sacrifice film is at least partially opened. The anchor portion has a first anchor provided to divide the movable electrode into a plurality of movable electrode units when viewed in a plan view such that one pair of adjacent movable electrode units of the plurality of movable electrode units divided share the same first anchor.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: June 13, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kimitoshi Sato
  • Method for fabricating semiconductor device
    Patent number: 9679816
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung