Abstract: A substrate intermediary body includes: a substrate having a hole in a thickness direction, and a conductor being disposed in the hole; and an adhesion layer formed on a wall surface of the hole. The adhesion layer contains a reaction product of a polymer (A) having a cationic functional group and having a weight-average molecular weight of from 2,000 to 1,000,000 and a polyvalent carboxylic acid compound (B) having two or more carboxyl groups per molecule or a derivative thereof.

Abstract: A method of manufacturing a light emitting device is provided. Multiple light-emitting elements are formed on a substrate in a first density. A first transferring process is performed to transfer the light emitting elements to a transition carrier. The light-emitting elements are disposed on the transition carrier in a second density. The first density is greater than the second density. Multiple electronic devices are disposed on the transition carrier in correspondence with the light-emitting elements. An encapsulation layer is formed on the transition carrier to cover the light emitting elements and the electronic devices. Portions of the encapsulation layer are removed to form multiple package units including the light-emitting elements and the electronic devices. A second transferring process is performed to transfer the package units to an array substrate. The encapsulation layer is removed to expose the light emitting elements and the electronic devices.

Abstract: A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

Abstract: Embodiments of the present disclosure generally relate to light emitting diodes LEDs and methods of manufacturing the LEDs. The LEDs include a mesa-structure that improves light extraction of the LEDs. Furthermore, the process for forming the LEDs refrains from using physical etching to a quantum well active region of the LEDs to prevent compromising performance at the quantum well sidewall.

Abstract: An organic light emitting diode display includes: a substrate; a scan line formed over the substrate and transmitting a scan signal; a data line crossing the scan line and transmitting a data voltage; a driving voltage line crossing the scan line and transmitting a driving voltage; a switching transistor connected to the scan line and the data line; a driving transistor connected to the switching transistor; a driving connection member connected to a driving gate electrode of the driving transistor; a storage capacitor including a first storage electrode and a second storage electrode; a pixel electrode electrically connected to the driving transistor; and a contact hole connecting the first storage electrode and the driving connection member. The second storage electrode may include a cut-out by a curved edge at least partially surrounding the contact hole, and the pixel electrode may be formed not to overlap the cut-out.

Abstract: A method for manufacturing a semiconductor thin film includes sequentially forming a first semiconductor layer, an intermediate layer, and a second semiconductor layer over a substrate. The first semiconductor layer and the second semiconductor layer can be one and another of an n-type semiconductor layer and a p-type semiconductor layer. At least one of the first semiconductor layer, the intermediate layer, or the second semiconductor layer is formed via a solution process. The n-type semiconductor layer can include indium oxide. The intermediate layer can include a self-assembly material. The p-type semiconductor layer can include a p-type organic semiconductor material, and can be pentacene. On the basis, a semiconductor thin film manufactured thereby, a semiconductor thin film transistor, and a display apparatus, are also disclosed.

Abstract: An image sensor includes a first light sensor layer including light sensing cells configured to sense first light of an incident light and generate electrical signals based on the sensed first light, and a color filter array layer disposed on the first light sensor layer, and including color filters respectively facing the light sensing cells. The image sensor further includes a second light sensor layer disposed on the color filter array layer, and configured to sense second light of the incident light and generate an electrical signal based on the sensed second light. Each of the color filters includes a nanostructure including a first material having a first refractive index, and a second material having a second refractive index greater than the first refractive index, the first material and the second material being alternately disposed with a period.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.

Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Abstract: Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer.

Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer.

Abstract: A method for manufacturing a MEMS element, including the following: forming a least one stationary weight element and at least one moving weight element in the MEMS element, and positioning at least one fixing element at the stationary weight element and at the moving weight element, the fixing element being formed so as to be able to be severed.

Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.

Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack over the semiconductor substrate. The first gate stack includes a metal electrode. The semiconductor device structure also includes a second gate stack over the semiconductor substrate, and the second gate stack includes a polysilicon element.

Abstract: A thin film transistor includes a gate electrode, an organic semiconductor overlapping the gate electrode, an insulator between the gate electrode and the organic semiconductor, and a source electrode and a drain electrode electrically connected to the organic semiconductor, respectively. The organic semiconductor is capable of being applied by a solution process, the insulator includes an inorganic insulating layer having a surface facing the organic semiconductor, and the surface includes a coating with a polysiloxane having an acrylic terminal group.

Abstract: A germanium photodetector which reduces a dark current without degradation of a photocurrent includes: a silicon substrate; a lower clad layer formed on the silicon substrate; a core layer formed on the lower clad layer; a p-type silicon slab formed in a part of the core layer and doped with a p-type impurity ion; p++ silicon electrode sections that are highly-doped with a p-type impurity and act as an electrode; and germanium layers which absorb light. The germanium photodetector further includes an upper clad layer, an n-type germanium region doped with an n-type impurity above the germanium layer, and an electrode. According to the present invention, two germanium layers are provided on the p-type silicon slab so as to miniaturize the area of the surface of the individual germanium layer in contact with the p-type silicon slab, so that the dark current due to threading dislocation can be reduced.