Patents Examined by Benjamin Tzu-Hung Liu
  • High-resolution three-dimensional profiling of features in advanced semiconductor devices in a non-destructive manner using electron beam scanning electron microscopy
    Patent number: 11139142
    Abstract: A plurality of energy filter values are obtained using a model that simulates potential distribution within a 3D feature when an electron beam of an SEM impinges on a selected area that includes the 3D feature. A correspondence is extracted between the plurality of energy filter values and respective depths of the 3D feature along a longitudinal direction by analyzing the simulated potential distribution. A plurality of SEM images of the 3D feature corresponding to the plurality of energy filter values are obtained. The plurality of SEM images are associated with their respective depths based on the extracted correspondence between the plurality of energy filter values and the respective depths. A composite 3D profile of the 3D feature is generated from the plurality of SEM images obtained from various depths of the 3D feature.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Ofer Yuli, Samer Banna
  • Electronic device packaging
    Patent number: 11133261
    Abstract: An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Chee Kheong Yoon, Jia Yan Go
  • Interconnect structure
    Patent number: 11133216
    Abstract: A nitridation treatment method is provided. The nitridation treatment method includes executing a nitridation treatment with respect to a hydrophobic surface defining an interconnect trench to convert the hydrophobic surface to a hydrophilic surface. The nitridation treatment method further includes depositing a seed layer including a conductive material and manganese on the hydrophilic surface. The nitridation treatment method also includes thermally driving all the manganese out of the seed layer to form a diffusion barrier including manganese at the hydrophilic surface. In addition, the nitridation treatment method includes filling remaining space in the interconnect trench with the conductive material to form an interconnect.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Roger A. Quon, Chih-Chao Yang
  • Metal cut patterning and etching to minimize interlayer dielectric layer loss
    Patent number: 11133189
    Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
  • Back biasing of FD-SOI circuit blocks
    Patent number: 11127738
    Abstract: A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: September 21, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, David Edward Fisch, Kenneth Duong, Xu Chang, Liang Wang
  • High electron mobility transistor devices and methods for forming the same
    Patent number: 11127846
    Abstract: A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first recess is located between the drain structure and the gate structure.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 21, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Transistor, semiconductor device, electronic apparatus, and method for producing transistor
    Patent number: 11127743
    Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Katsuhiko Takeuchi, Masashi Yanagita, Shinichi Wada
  • 3D graphene transistor
    Patent number: 11121334
    Abstract: A field effect transistor having a channel that comprises three-dimensional graphene foam. The subject matter of the invention concerns a three dimensional field-effect transistor having a channel based on graphene foam and the use of ionic liquid as a gate. The graphene foam is made of a three-dimensional network of single and double layer graphene that extends in all the three dimensions. Metal contacts on either end of the graphene foam form the drain and source contacts of the transistor.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 14, 2021
    Assignee: Trustees of Tufts College
    Inventors: Sameer Sonkusale, Shideh Kabiri Ameri Abootorabi, Pramod Kumar Singh
  • Semiconductor device
    Patent number: 11114562
    Abstract: A semiconductor device includes: a first gate structure on a substrate; a first drain region having a first conductive type adjacent to one side of the first gate structure; a source region having the first conductive type adjacent to another side of the first gate structure; and a first body implant region having a second conductive type under part of the first gate structure.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Photodiode
    Patent number: 11114634
    Abstract: A photodiode according to example embodiments includes an anode, a cathode, and an intrinsic layer between the anode and the cathode. The intrinsic layer includes a P-type semiconductor and an N-type semiconductor, and composition ratios of the P-type semiconductor and the N-type semiconductor vary within the intrinsic layer depending on a distance of the intrinsic layer from one of the anode and the cathode.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Bae Park, Kyu Sik Kim, Yong Wan Jin, Kwang Hee Lee, Dong-Seok Leem, Seon-Jeong Lim
  • Semiconductor memory devices including separate upper and lower bit line spacers
    Patent number: 11088148
    Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daeik Kim, Semyeong Jang, Jemin Park, Yoosang Hwang
  • Power converter
    Patent number: 11088630
    Abstract: In a power converter, busbars are connected to respective power terminals. The power terminals include at least one narrow power terminal. The at least one narrow power terminal includes a first portion having a first thermal resistance and a first rigidity, and a second portion having a second thermal resistance and a second rigidity, the second thermal resistance being higher than the first thermal resistance, the second rigidity being smaller than the first rigidity.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 10, 2021
    Assignee: DENSO CORPORATION
    Inventors: Kazuharu Tochikawa, Shintaro Kogure
  • Semiconductor device and method for fabricating the same
    Patent number: 11063135
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
  • Display device
    Patent number: 11037484
    Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver, in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 15, 2021
    Inventors: Bon-Yong Koo, Dong Yeon Son
  • Vertical microbolometer contact systems and methods
    Patent number: 11031432
    Abstract: Systems and methods are directed to vertical legs for an infrared detector. For example, an infrared imaging device may include a microbolometer array in which each microbolometer includes a bridge and a vertical leg structure that couples the bridge to a substrate such as a readout integrated circuit. The vertical leg structure may run along a path that is parallel to a plane defined by the bridge and may be oriented perpendicularly to the plane. The path may be disposed within, below, or above the plane defined by the bridge.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 8, 2021
    Assignee: FLIR Systems, Inc.
    Inventors: James L. Dale, Christopher Chan, Eric A. Kurth
  • Micro light emitting diode with remnants of fabrication substrate for structural support
    Patent number: 11011687
    Abstract: A light emitting diode (LED) device includes a semiconductor layer and one or more portions of a wafer on which the semiconductor layer was formed, the other portions of the wafer having been removed by an etching process. The semiconductor layer has a front surface that includes a light emitting area. The remnants of the wafer on which the semiconductor layer are disposed on the front surface of the semiconductor layer and define a trench. The trench is positioned such that the light emitting area emits light into the trench. The remnants of the wafer make the LED device more robust and the trench may reduce crosstalk with adjacent LED devices.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 18, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Allan Pourchet, Pooya Saketi, Daniel Brodoceanu, Oscar Torrents Abad
  • Memory device
    Patent number: 11011580
    Abstract: According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 18, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Kenichi Murooka
  • Semiconductor device package and a method of manufacturing the same
    Patent number: 11004779
    Abstract: A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: May 11, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Shu Peng, Cheng-Lin Ho, Chih-Cheng Lee
  • Laser-induced selective heating for microLED placement and bonding
    Patent number: 10998286
    Abstract: A laser is used to induce bonding of LED contact pads with corresponding substrate contact pads on a display substrate. The wavelength of the laser light and the material used for the contact pads are both selected so that the laser light is capable of melting the contact pads. For example, the laser light has a wavelength of between 220 nm and 1200 nm, and the contact pads are formed of a copper-tin oxide (CuSn). Furthermore, the system may be configured to shine the laser light through a number of other components, such as the pick-up head and the LED itself. These materials can be formed of materials that do not absorb the energy of the laser light. Bonding the contacts with a laser in this manner allows for faster heating and cooling times, avoids reheating of previously bonded contact pads, and reduces thermal expansion of the display substrate.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 4, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Daniel Brodoceanu, Allan Pourchet, Oscar Torrents Abad
  • Semiconductor device and method of manufacturing the same
    Patent number: 10978472
    Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seung Jun Lee