Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Abstract: The present invention provides a method for fabricating a fluoride phosphor. A first solution is formed by dissolving potassium fluoride (KF) and either K2MnF6 or KMnO4 in a hydrofluoric acid solution. A second solution is formed by mixing a surfactant and a silane. The first solution and the second solution are mixed to form a precipitate. The precipitate is collected after the first solution and the second solution are mixed. The present invention also provides a fluoride phosphor represented by the following formula: K2[SiF6]:Mn4+. The fluoride phosphor has a particle size in a range of about 1 ?m to about 10 ?m. The present invention further provides a light-emitting apparatus and backlight module employing the same.

Abstract: An optoelectronic component includes a housing that includes a rectangular basic shape with four sides. The sides each merge into one another at a corner point. At least two carrier arms of two contact elements of a lead frame are guided to an edge of the housing. The two carrier arms are arranged on different sides of the housing. The two carrier arms are each at different spacings from the two corner points of the side on which the carrier arms are arranged. The spacings differ at least in the width of a carrier arm.

Abstract: An optoelectronic semiconductor device comprises a substrate; a semiconductor system including a first conductivity layer, a second conductivity layer, and a conversion unit between the first conductivity layer and the second conductivity layer, wherein the first conductivity layer is closer to the substrate than the second conductivity layer is to the substrate, and the second conductivity layer comprises a top surface perpendicular to a thickness direction of the semiconductor system, and in a top view of the semiconductor system, an outline of the first conductivity layer surrounds an outline of the second conductivity layer; a first electrical connector on the first conductivity layer of the semiconductor system; a second electrical connector comprising a shape formed on the second conductivity layer of the semiconductor system; and a contact layer formed on the top surface of the second conductivity layer and having an outer perimeter at an inner side of the outline of the second conductivity layer in th

Abstract: The light emitting element is provided to comprise: a first conductive type semiconductor layer; a mesa; a current blocking layer; a transparent electrode; a first electrode pad and a first electrode extension; a second electrode pad and a second electrode extension; and an insulation layer partially located on the lower portion of the first electrode, wherein the mesa includes at least one groove formed on a side thereof, the first conductive type semiconductor layer is partially exposed through the groove, the insulation layer includes an opening through which the exposed first conductive type semiconductor layer is at least partially exposed, the first electrode extension includes extension contact portions in contact with the first conductive type semiconductor layer through an opening, and the second electrode extension includes an end with a width different from the average width of the second electrode extension.

Abstract: Disclosed is a photoelectric conversion element for converting light into electric energy, including a first electrode, a second electrode, and at least one organic layer existing therebetween, the organic layer containing a compound represented by the general formula (1): wherein R1 to R4 are alkyl groups, cycloalkyl groups, alkoxy groups, or arylether groups, which may be respectively the same or different; R5 and R6 are halogens, hydrogens, or alkyl groups, which may be respectively the same or different; R7 is an aryl group, a heteroaryl group, or an alkenyl group; M represents an m-valent metal and is at least one selected from boron, beryllium, magnesium, aluminum, chromium, iron, nickel, copper, zinc, and platinum; L is selected from halogen, hydrogen, an alkyl group, an aryl group, and a heteroaryl group; and m is in a range of 1 to 6 and, when m?1 is 2 or more, each L may be the same or different.

Abstract: A wiring substrate includes a first reinforcement pattern stacked on a lower surface of a first insulation layer at a peripheral region located at an outer side of a wiring formation region. A first reinforcement via extends through a second insulation layer in the thickness-wise direction and contacts the first reinforcement pattern. A second reinforcement pattern is stacked on a lower surface of the second insulation layer and connected to the first reinforcement pattern by the first reinforcement via. The first reinforcement via includes a top that partially extends into the first insulation layer.

Abstract: A display may include a color filter layer, a liquid crystal layer, and a thin-film transistor layer. A camera window may be formed in the display to accommodate a camera. The camera window may be formed by creating a notch in the thin-film transistor layer that extends inwardly from the edge of the thin-film transistor layer. The notch may be formed by scribing the thin-film transistor layer around the notch location and breaking away a portion of the thin-film transistor layer. A camera window may also be formed by grinding a hole in the display. The hole may penetrate partway into the thin-film transistor layer, may penetrate through the transistor layer but not into the color filter layer, or may pass through the thin-film transistor layer and partly into the color filter layer.

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Abstract: A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.

Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.

Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Abstract: Disclosed is a curable resin composition that has significantly high transparency in the UV region, UV resistance and heat resistance, does not cause cracking, peeling or coloration even when used for sealing a UV LED to which high power is applied, and inhibits shrinking during curing. The curable resin composition includes 20-85 wt % of an alkoxy oligomer having a specific structure and present as liquid at room temperature and 15-80 wt % of a silicone resin present as solid at room temperature. The curable resin composition preferably includes 0.1-20 parts by weight of phosphoric acid, as a catalyst, based on 100 parts by weight of the combined weight of the alkoxy oligomer and the silicone resin.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

Abstract: A sensor device includes a semiconductor chip. The semiconductor chip has a sensing region sensitive to mechanical loading. A pillar is mechanically coupled to the sensing region.

Abstract: A method of operating a microwave oven and a microwave oven are disclosed. The microwave oven comprises a magnetron for providing microwave power to heat a load placed in the microwave oven, and a solid-state microwave generator for providing microwave power to sense presence and/or determine nature of the load in the microwave oven.

Abstract: A display includes: a first light emitting layer to be transferred to a first region on a substrate; a second light emitting layer to be transferred to a second region on the substrate; and a level-difference forming member forming a first level difference between the first region and the second region, the first level difference suppressing attachment of the first light emitting layer to the second region when the first light emitting layer is transferred to the first region.

Abstract: The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.