Abstract: Spin-on HSQ is employed to gap fill patterned metal layers in manufacturing ultra high density, multi-metal layer semiconductor devices. The degradation of deposited HSQ layers during formation of borderless vias, as from photoresist stripping using an O.sub.2 -containing plasma, is significantly reduced or prevented by including hydrogen in the stripping plasma. Embodiments include stripping in a plasma containing a sufficient amount of a forming gas (H.sub.2 /N.sub.2) to prevent reduction of the number of Si--H bonds of the deposited HSQ gap fill layer below about 70%, before and after solvent cleaning.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation. A substrate having a plurality of active regions, including a large active region and a small active region, is provided. A silicon nitride layer is formed on the substrate. A shallow trench is formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trench is filled therewith. A partial reverse active mask is formed on the oxide layer, so that the oxide layer on a central part of the large active region is exposed. Whereas, the oxide layer on an edge part of the large active region and on the small active region are covered by the partial reverse active mask. The oxide layer is etched with the silicon nitride layer as a stop layer, using the partial reverse active mask as a mask. The oxide layer is planarized until the oxide layer within the shallow trench has a same level as the silicon nitride layer.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: Proposed is a technique for determining the suitability of use of a material for an electroless plating operation. A solution including the material is subject to an anodic linear sweep voltammetric measurement. The resulting anodic peak is compared with that of a control solution in order to evaluate the potential of the material for poisoning a factory plating bath.

Abstract: A chemical mechanical polishing slurry comprising a film forming agent, an oxidizer, a complexing agent and an abrasive, and a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, and titanium nitride containing layers from a substrate.

Abstract: The quartz shadow ring of a conventional plasma etching apparatus is desirably coated with material which inhibits the liberation of oxygen into the plasma. Investigation has shown that the liberated oxygen degrades etching uniformity across the wafer.

Abstract: Disclosed are metal fuse structures and methods for making the same. The method includes forming the fuse structure from a metallization layer. Depositing a bottom oxide layer, that is an HDP oxide, over the fuse structure that is formed from the metallization layer. Depositing a doped oxide layer over the base oxide layer. Depositing a top oxide layer over the doped oxide layer. Etching through the top oxide layer. Detecting an increased level of a dopant species that is emitted when the doped oxide layer begins to etch. The method further includes terminating the etching when the increased level of dopant species is detected. Wherein at least the bottom oxide layer remains over the fuse structure that is formed from the metallization layer.

Abstract: A carrier for surface plasmon resonance is prepared by coating a silver layer on the carrier surface, followed by heating the material for a time sufficient to anneal it.

Abstract: According to the present invention, in the growth of an oxide single crystal or a compound semiconductor single crystal such as GaAs single crystal by the CZ method or LEC method, the tendency of concave solid-liquid interface shape at the periphery of the growing crystal can be suppressed to prevent polycrystallization without localized heating of the solid-liquid interface, while controlling the diameter of the growing crystal even when using a crucible with a larger diameter, thus improving the yield of crystal on a commercial scale. In the invention, the end of a cylindrical body having an inner diameter of larger than the predetermined diameter of straight part of the growing crystal is immersed in the raw material melt or liquid encapsulant and the crystal is pulled while preventing the shape of the solid-liquid interface from becoming concave by controlling the rotation rate of at least one of a crucible holding the raw material melt, the growing crystal and cylindrical body.

Abstract: A method of forming an atomizing spray nozzle includes the steps of etching a swirl chamber and a spray orifice in a thin sheet of material. The swirl chamber is etched in a first side of the disk and the spray orifice is etched through a second side to the center of the swirl chamber. Feed slots are etched in the first side of the disk extending non-radially to the swirl chamber such that liquid can be conveyed to the swirl chamber so as to create and sustain the swirling motion. A inlet piece with inlet passage therein is connected with first side of the disk so as to convey liquid to the feed slots of the disk and to enclose the feed slots and swirl chamber. In addition to the method described an atomizing spray nozzle having the configuration described is much improved in its spray characteristics. The present invention also provides a method of forming a number of spray nozzles simultaneously in a single manufacturing process.

Abstract: Atomized metal is deposited metal onto a substrate so as to cause at least partial solidification of the deposited metal; further atomized metal is deposited onto the partially solidified deposited metal on the substrate; and the metal deposited onto the partially solidified deposited metal is allowed to fully solidify on the substrate; the cooling of the further deposited metal, and the composition of the metal and/or of a gas used in the atomization of the further atomized metal being tailored such that volumetric contraction on solidification and cooling of the further deposited metal is compensated for, when the deposited metal has been cooled to ambient temperature, by volumetric expansion in a reaction or phase change in the further deposited metal.

Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

Abstract: A wet etching method for making calibration bump disks for use in providing quality control of production run magnetic hard disks is disclosed. It includes the steps of: (a) coating a layer of bump material on a substrate; (b) coating a photoresist layer on the layer of bump material; (c) exposing the photoresist layer to a light source under a photomask; (d) developing the photoresist layer using a developer solution to form an undeveloped photoresist layer; (e) etching the substrate containing the layer of bump material and the undeveloped photoresist layer to remove portions of the layer of bump material not covered by the undeveloped photoresist layer; and (f) stripping the undeveloped photoresist layer to leave at least a bump on the substrate which was originally covered by the undeveloped photoresist layer. The wet etching method eliminates many of the problems observed from the conventional metal mask method, including the elimination of the convex-shaped bump surface.

Abstract: A wafer backing insert for use in a free mount semiconductor polishing apparatus and process is disclosed wherein the wafer backing insert behind the semiconductor substrate has a diameter less than the diameter of the semiconductor substrate being polished to allow the removal of material at the edge of the substrate to be less than the overall average removal of material across the entire substrate. In a preferred embodiment, the process of the present invention utilizing a wafer backing insert having a diameter less than the diameter of the semiconductor substrate being polished is used in combination with a first polishing step utilizing a conventional wafer backing insert to control the resulting thickness and overall TTV of the polished substrate.

Abstract: A method for producing a thin film or nanoparticle deposit includes the step of providing a working liquid, movement of the working liquid at a liquid surface prevented by surface tension. The method also includes the steps of supplying an electric charge having a first polarity to the working liquid at the liquid surface to overcome surface tension at the liquid surface to produce a first plurality of charged nanodrops and directing the first plurality of charged nanodrops against a substrate surface. The method further includes the steps of supplying an electric charge having a second polarity to the working liquid at the liquid surface, the second polarity being opposite to the first polarity, to overcome surface tension at the liquid surface to produce a second plurality of charged nanodrops, and directing the second plurality of charged nanodrops against the substrate surface.

Abstract: A method for fabricating a semiconductor device at low cost is provided in which a mask layer having a very large polishing selection ratio is used as a polishing stop film by forming the polishing stop film in self-alignment. An object layer to be flattened is formed on a substrate. The object layer contains an irregularity. A polishing stop film which is polished at a slower rate and a mask layer which is polished at about the same rate as the object layer are deposited on the object layer. Then, the mask layer on a high level portion of the object layer is removed by chemical-mechanical polishing. The polishing stop film is etched other than under the mask layer, so that the polishing stop film at the high level portion and side wall of the step is removed.

Abstract: The present invention relates to wear-through detection in multilayered parts. This invention specifically encompasses, in one aspect, wear-through detection in semiconductor vacuum processing systems in which a wear indicator that will release a detectable constituent upon exposure to processing conditions is used inside the semiconductor vacuum processing tool. This invention permits real time detection of wear during operation of semiconductor vacuum processing equipment.

Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.

Abstract: A soft-landing etch process is provided to form an oxide layer with uniform thickness on an open area between flash memory transistors on a substrate. A dielectric oxide layer, such as silicon dioxide, is formed on a semiconductor substrate. A polysilicon layer used to form gates of flash memory transistors is then formed on the oxide layer. The polysilicon layer is covered with a layer of conductive material, such as tungsten silicide (WSi). A cap polysilicon layer is deposited on the conductive layer. An anti-reflecting coating, such as SiON, is formed on the cap polysilicon layer. A photo-resist mask comprising a pattern defining a gate is formed on the surface of the anti-reflecting coating. The softlanding etch process performed to expose oxide layer on the substrate area between flash memory transistors includes three etch steps. The first etch step is carried out to remove materials covering the gate polysilicon layer on the area between flash memory transistors.

Abstract: The present invention aims to provide a continuous forming method and apparatus for functional deposited films having excellent characteristics while preventing any mutual mixture of gases between film forming chambers having different pressures, wherein each of semiconductor layers of desired conduction type is deposited on a strip-like substrate within a plurality of film forming chambers, by plasma CVD, while the strip-like substrate is being moved continuously in a longitudinal direction thereof through the plurality of film forming chambers connected via a gas gate having the structure of introducing a scavenging gas into a slit-like separation passage, characterized in that at least one of the gas gates connecting the i-type layer film forming chamber for forming the semiconductor junction and the n- or p-type layer film forming chamber having higher pressure than the i-type layer film forming chamber has the scavenging gas introducing position disposed on the n- or p-type layer film forming chamber sid