Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.

Abstract: A method of manufacturing a curved-surface detector includes: slimming a sensor substrate having photoelectric devices arranged therein to a predetermined thickness; seating the sensor substrate slimmed to the predetermined thickness on a jig curved so as to have a curved-surface shape such that the sensor substrate is curved so as to have a curved-surface shape; and joining a flexible scintillator substrate configured to emit light when being struck by radiation to an upper surface of the sensor substrate such that curvature of the sensor substrate curved so as to have a curved-surface shape by the jig is maintained.

Abstract: A method includes forming a trench in a low-K dielectric layer, where the trench exposes an underlying contact area of a substrate. A first tantalum nitride (TaN) layer is conformally deposited within the trench, where the first TaN layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A tantalum (Ta) layer is deposited on the first TaN layer conformally within the trench, where the Ta layer is deposited using physical vapor deposition (PVD). An electroplating process is performed to deposit a conductive layer over the Ta layer. A via is formed over the conductive layer, where forming the via includes depositing a second TaN layer within the via and in contact with the conductive layer.

Abstract: Provided is a disclosure relating to a method for manufacturing an organic solar cell comprising providing a substrate; forming a first electrode on the substrate; forming a photoactive layer by coating a solution comprising a photoactive material and a solvent on the first electrode; drying the photoactive layer in a closed drying system having a constant volume; and forming a second electrode on the photoactive layer, and an organic solar cell manufactured using the same.

Abstract: Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

Abstract: A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.

Abstract: Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.

Abstract: A display apparatus comprises a light-emitting device on a device substrate; an encapsulating layer on the device substrate and covering the light-emitting device; an encapsulation substrate on the encapsulating layer and including a plurality of penetrating holes disposed at a regular interval; and a moisture-blocking layer between the encapsulating layer and the encapsulation substrate and including a plurality of moisture-absorbing particles dispersed in the encapsulating layer, wherein the moisture-blocking layer has a water vapor transmission rate lower than that of the encapsulating layer.

Abstract: A stretchable display device capable of being stretched or contracted by external force is discussed. The stretchable display device includes a stretchable substrate capable of being stretched or contracted and divided into a display area and a non-display area, a plurality of organic light emitting diode (OLED) panels disposed in the display area of the stretchable substrate at a constant interval, a plurality of data link lines, a first constant voltage link line and a second constant voltage link line disposed in the non-display area of the stretchable substrate and connected to each of the OLED panels, and a plurality of stretchable lines disposed inside the stretchable substrate in a predetermined shape.

Abstract: A display apparatus includes a plurality of pixels each including a substrate on which are disposed: an interlayer insulating layer; a driving thin film transistor in which a driving semiconductor layer and a driving gate electrode are each disposed between the substrate and the first interlayer insulating layer; a first capacitor in which a first electrode, a first dielectric pattern and a second electrode are sequentially stacked, the first electrode being connected to the driving gate electrode; and a plurality of contact plugs extended through a thickness of the interlayer insulating layer, with which the driving thin film transistor and the first capacitor are respectively connected to electrodes outside thereof. Lateral surfaces of the first dielectric pattern are covered by the interlayer insulating layer, and the first dielectric pattern within the first capacitor is disposed spaced apart from each of the contact plugs.

Abstract: A fin-type semiconductor device includes a semiconductor structure having a plurality of fins formed in a substrate and a plurality of trenches each disposed between two adjacent fins, a spacer in each of the trenches, and an etch stop layer disposed below an upper surface of the spacer.

Abstract: An embodiment is a method. The method includes: dispensing a plurality of precursor materials over a collective wafer platter holding a plurality of wafers; heating the collective wafer platter while dispensing the precursor materials; rotating the collective wafer platter around a first axis while dispensing the precursor materials and heating the collective wafer platter; rotating the wafers around respective second axes while dispensing the precursor materials and heating the collective wafer platter, the first axis different from each of the second axes; and singulating integrated circuit devices from each of the wafers.

Abstract: The present disclosure provides an oxide semiconductor layer and a preparation method thereof, device, substrate, and means, and belongs to the field of semiconductor technologies. The method includes: forming an oxide semiconductor layer having multiply types of regions on a substrate, at least two types of the multiple types of regions having different thicknesses, and adjusting an oxygen content of at least one type of regions in the multiply types of regions, so that the oxygen content and the thickness in the multiple types of regions are positively correlated.

Abstract: A semiconductor device includes a semiconductor substrate having a body layer arranged between a front side and a drift layer, and forming a pn-junction with the drift layer. A front metallization is on the front side in Ohmic connection with the body layer, and a back metallization opposite is in Ohmic connection with the drift layer. An IGBT cell region of the device includes a plurality of gate electrodes in Ohmic connection with a gate metallization. Each gate electrode is electrically insulated from the semiconductor substrate by a respective gate dielectric extending through the body layer. A free-wheeling diode region of the device includes a plurality of field electrodes in Ohmic connection with the front metallization. Each field electrode is separated from the semiconductor substrate by a respective field dielectric extending through the body layer. Additional semiconductor device embodiments are described.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract: An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction.

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.