Patents Examined by Bo B Jang
  • Patent number: 11145606
    Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 12, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
  • Patent number: 11145561
    Abstract: The present disclosure provides a display panel and a method for manufacturing the same. The method includes providing a substrate including a display area and a non-display area. A chip on film (COF) and a testing structure are disposed in the non-display area. A testing circuit includes a signal trace including a non-metal trace and a metal trace connecting to each other. A cutting line is disposed on the signal trace. The method further includes testing the display area of the substrate by the testing structure, and removing a test pad.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Xing Ming, Caiqin Chen, Yiyi Wang
  • Patent number: 11126048
    Abstract: An array substrate includes gate lines, data lines, and pixel units defined by adjacent gate lines and adjacent data lines, the gate lines, the data lines, and the pixel units being formed on a substrate, wherein the gate line gradually becomes wider from a driving start end to a driving terminal end. on the array substrate.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 21, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hao Chu, Yue Shi, Chuanbao Chen
  • Patent number: 11121287
    Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a carrier having a pedestal with a support surface, applying a liquid joining material with filler particles to the support surface of the pedestal and applying a radiation emitting semiconductor chip with a mounting surface, which is larger than the support surface of the pedestal to the liquid joining material such that the joining material forms a joining layer between the support surface of the pedestal and the mounting surface of the semiconductor chip and the joining material at least partially fills only a recess, which is limited by a part of the mounting surface projecting beyond the support surface.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 14, 2021
    Assignee: OSRAM OLED GMBH
    Inventor: Ivar Tangring
  • Patent number: 11114473
    Abstract: A method for transferring light emitting elements precisely during manufacture of display panels includes providing light emitting elements; providing a first electromagnetic plate defining magnetic adsorption positions; providing a receiving substrate defining receiving areas; providing a second electromagnetic plate; energizing the first electromagnetic plate to magnetically adsorb one light emitting element at one adsorption position; providing a second electromagnetic plate; and transferring the light emitting elements to one receiving area of the receiving substrate.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 7, 2021
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Po-Liang Chen, Yung-Fu Lin
  • Patent number: 11114541
    Abstract: Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 7, 2021
    Inventors: Sunmin Moon, Young-Lim Park, Kyuho Cho, Hanjin Lim
  • Patent number: 11114570
    Abstract: A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.
    Type: Grant
    Filed: April 12, 2020
    Date of Patent: September 7, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Ching-Fu Lin, Zong-Xuan Li, Wei-Tsung Chen
  • Patent number: 11114514
    Abstract: An organic electroluminescent display panel is provided, including a pixel defining layer. The pixel defining layer includes a plurality of openings and a bank surrounding each of the plurality of openings and defining a plurality of pixel areas. The bank is composed of a hydrophilic material pattern layer and a conductive hydrophobic pattern layer which are stacked from bottom to top.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 7, 2021
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kui Gong, Xianxue Duan, Zhihai Zhang
  • Patent number: 11107843
    Abstract: An array substrate includes a substrate, a dual-gate oxide thin film transistor TFT, an electrode for display and a polycrystalline silicon TFT. The dual-gate oxide thin film transistor TFT and the electrode for display are located in a sub-pixel on the substrate, and a drain electrode of the dual-gate oxide TFT is electrically connected to the electrode for display.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: August 31, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lianjie Qu, Bingqiang Gui, Yonglian Qi, Hebin Zhao, Yun Qiu, Dan Wang
  • Patent number: 11107679
    Abstract: Methods of processing a target material are disclosed. In one arrangement, a multilayer structure is irradiated with a radiation beam. The multilayer structure comprises at least a target layer comprising the target material and an additional layer not comprising the target material. The additional layer is metallic. The target layer is irradiated through the additional layer during the irradiation of the multilayer structure. A transfer of energy from the radiation beam to the target layer and to the additional layer is such as to cause a thermally-induced change in the target layer. The thermally-induced change comprising one or more of: crystal growth in the target material, increased carrier mobility in the target material, increased chemical stability in the target material, and increased uniformity of electrical properties in the target material.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 31, 2021
    Assignee: National University of Ireland, Galway
    Inventors: Gerard O'Connor, Nazar Farid, Pinaki Das Gupta
  • Patent number: 11101218
    Abstract: Some embodiments include an integrated assembly which has a semiconductor material with a surface. A first layer is over and directly against the surface. The first layer includes oxygen and a first metal. The relative amount of oxygen to the first metal is less than or equal to an amount sufficient to form stoichiometric metal oxide throughout the first layer. A second metal is over and directly against the first layer. A second layer is over and directly against the second metal. The second layer includes nitrogen and a third metal. Some embodiments include an integrated assembly which has a semiconductor material with a surface. A metal is adjacent the surface and is spaced from the surface by a distance of less than or equal to about 10 ?. There is no metal germanide or metal silicide between the metal and the surface.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sumeet C. Pandey, Gurtej S. Sandhu
  • Patent number: 11094546
    Abstract: A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 17, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Delphine Longrie, David Kurt de Roest
  • Patent number: 11094712
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 17, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Patent number: 11088181
    Abstract: The present application discloses a method of fabricating an array substrate. The method includes forming a first conductive material layer on a base substrate; forming an insulating layer on a side of the first conductive material layer distal to the base substrate, the insulating layer formed to cover a first part of the first conductive material layer, exposing a second part of the first conductive material layer; over-etching the first conductive material layer to remove the second part of the first conductive material layer, and remove a portion of a periphery of the first part of the first conductive material layer to form a recess between the insulating layer and the base substrate, thereby forming a first electrode; and subsequent to forming the first electrode and the recess, annealing the insulating layer to mobilize a portion of the insulating layer above the recess and fill the recess with a mobilized insulating material.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 10, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Beijing BOE Display Technology Co., Ltd.
    Inventors: Lianjie Qu, Bingqiang Gui, Yonglian Qi, Guangdong Shi, Shuai Liu, Hebin Zhao
  • Patent number: 11081591
    Abstract: A semiconductor device includes a substrate, a first semiconductor auxiliary film, a semiconductor film, a gate insulating film, and a gate electrode. The first semiconductor auxiliary film is provided in a selective region on the substrate. The semiconductor film includes an oxide semiconductor material, and has a low-resistive region in contact with the first semiconductor auxiliary film and a channel region provided in a portion different from the low-resistive region. The gate insulating film covers the semiconductor film from the channel region to at least part of the low-resistive region. The gate electrode is opposed to the channel region of the semiconductor film via the gate insulating film.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 3, 2021
    Assignee: JOLED INC.
    Inventor: Yasuhiro Terai
  • Patent number: 11081028
    Abstract: A light-emitting device assembly includes a light-emitting device including a light-emitting layer, a first electrode, and a second electrode, and a first connecting portion and a second connecting portion provided on a base, in which the first connecting portion and the second connecting portion are separated from each other by a separation portion, the base is exposed from the separation portion, a wide portion is on a first connecting portion side of the separation portion, the first electrode includes a first portion and a second portion, the second portion of the first electrode is connected to the first connecting portion, the first portion of the first electrode extends from the second portion of the first electrode, and an orthographic projection image of the first portion of the first electrode with respect to the base and the wide portion of the separation portion overlap with each other at least in part.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: August 3, 2021
    Assignee: SONY CORPORATION
    Inventors: Akira Ohmae, Yusuke Kataoka, Tatsuo Ohashi, Sayaka Aoki, Hiroki Naito, Ippei Nishinaka, Tsuyoshi Sahoda, Toshio Fujino, Hideyuki Nishioka, Goshi Biwa
  • Patent number: 11075356
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided, which pertain to the field of display technologies. The display substrate includes a display area and a package area surrounding the display area. The display substrate includes a base substrate and an interlayer insulating layer on the substrate. The interlayer insulating layer has a groove, an orthographic projection of the groove on the base substrate is located within an orthographic projection of the package area on the base substrate, and the groove is provided with a sealing material.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 27, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Fashun Li, Dan Jia, Longlong Yang
  • Patent number: 11075149
    Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seokhyun Lee
  • Patent number: 11069839
    Abstract: Disclosed is an optical component package. The optical component package according to the present invention includes: a main substrate including a plurality of metal bodies, and a vertical insulation part provided between the metal bodies; a sub-substrate provided in a cavity of the main substrate, and electrically connected to each of the metal bodies with the vertical insulation part interposed therebetween; an optical component mounted on the sub-substrate; and a light transmitting member provided above the optical component, wherein the sub-substrate includes: an insulating body; a via hole vertically passing through the insulating body, and filled with a metal material; and a metal pad connected to the optical component.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 20, 2021
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Moon Hyun Kim
  • Patent number: 11069665
    Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 20, 2021
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Mengzhi Pang, Rohan U. Mandrekar