Abstract: A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

Abstract: A converter layer bonding device, and methods of making and using the converter layer bonding device are disclosed. A converter layer bonding device as disclosed herein includes a release liner and an adhesive layer coating the release liner, the adhesive layer is solid and non-adhesive at room temperature, and is adhesive at an elevated temperature above room temperature.

Abstract: An MRAM device is provided. The MRAM device includes a first electrode, an MRAM stack formed on the first electrode, a hardmask structure formed on the MRAM stack, and a second electrode formed on the hardmask structure. A width of an upper portion of the hardmask structure is less than a width of the MRAM stack.

Abstract: A semiconductor package assembly includes a first mounting surface of a package substrate that faces a second mounting surface of a printed circuit board. A first structural element bond pad is mounted to the first mounting surface. A second structural element bond pad is mounted to the second mounting surface, and the first and second structural element bond pads are aligned with each other. A structural element is interconnected with a first solder joint to the first structural element bond pad and interconnected with a second solder joint to the second structural element bond pad. The structural element extends between the first and second structural element bond pads to absorb mechanical shock when a compressive force pushes one of the first and second mounting surfaces toward the other.

Abstract: A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the fourth gate structure.

Abstract: A display device includes a drive circuit on an insulating substrate; a connecting electrode electrically connected to the drive circuit; an LED element electrically connected to the drive circuit via the connecting electrode, and a first light reflecting layer overlapping the LED element and having an inclined surface. The inclined surface reflects light incident on the inclined surface through the LED element toward the connecting electrode. The first light reflecting layer may have a reflectance of 90 percent or more for light at a wavelength of 1.0 ?m or more to 1.5 ?m or less.

Abstract: A semiconductor device includes a substrate, a first thin-film transistor, and a second thin-film transistor. The first and second thin-film transistors are disposed on the substrate. The first thin-film transistor includes stacked first and second metal oxide layers. An oxygen concentration of the first metal oxide layer is less than an oxygen concentration of the second metal oxide layer, and a thickness of the second metal oxide layer is less than a thickness of the first metal oxide layer. A two-dimensional electron gas is located at an interface between the first and second metal oxide layers. The second thin-film transistor is electrically connected to the first thin-film transistor. The second thin-film transistor includes a third metal oxide layer. The second and third metal oxide layers belong to a same patterned layer.

Abstract: Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizontal portion and a vertical portion on top of the horizontal portion; a selector underneath the horizontal portion of the L-shaped phase change element; a top electrode in contact with a top surface of the vertical portion of the L-shaped phase change element; and a bottom electrode in contact with the selector; and a second PCM cell. A method of manufacturing the PCM device is also provided.

Abstract: According to an aspect of the present disclosure, the display device includes: a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate. The display device also includes a plurality of second substrates coupling first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of pixels disposed on the plurality of first substrates. The display device also includes a plurality of connection lines disposed on the plurality of second substrates and coupling the plurality of pixels. The display device further includes a protection layer disposed on each of the plurality of pixels.

Abstract: A display panel and a method for manufacturing the same are provided. The display panel includes a first bonding area and a second bonding area connected to the first bonding area. The display panel further includes a substrate and a bonding wiring layer. A thickness of a part of the substrate in the second bonding area is less than a thickness of a part of the substrate in the first bonding area. The bonding wiring layer is disposed on surfaces of the parts of the substrate in the first bonding area and the second bonding area. A side surface of the bonding wiring layer away from the first bonding area and a side surface of the substrate away from the first bonding area are located on a same plane.

Abstract: A display device includes: a substrate including a pixel area; and a pixel in the pixel area, the pixel including a first sub-light emitting area, a second sub-light emitting area, and a peripheral area surrounding the first and second sub-light emitting areas. The pixel may include: a first electrode, a second electrode, a third electrode, and a fourth electrode that are spaced from each other; a plurality of light emitting elements in the first and second sub-light emitting areas; a bank in the peripheral area and including a first opening corresponding to the first sub-light emitting area and a second opening corresponding to the second sub-light emitting area; and an intermediate bank between the first sub-light emitting area and the second sub-light emitting area and partially overlapping the second and third electrodes in a plan view.

Abstract: A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed.

Abstract: A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.

Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.

Abstract: A spin-transfer torque (STT) magnetoresistive memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer having a fixed magnetization direction, a free layer stack, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer stack. The free layer stack has a total thickness of less than 2 nm, and contains in order, a proximal ferromagnetic layer located proximal to the nonmagnetic tunnel barrier layer, a first non-magnetic metal sub-monolayer, an intermediate ferromagnetic layer, a second non-magnetic metal sub-monolayer, and a distal ferromagnetic layer.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.

Abstract: In embodiments, methods of configuring a molecular beam epitaxy system include providing a rotation mechanism configured to rotate a substrate deposition plane of a substrate around a center axis of the substrate deposition plane. A positioning mechanism is provided, being configured to allow the substrate deposition plane and an exit aperture of at least one material source in a plurality of material sources to be adjusted in position relative to each other between production runs. The at least one material source has a predetermined material ejection spatial distribution with a symmetry axis that intersects the substrate at a point offset from the center axis. A size of a reaction chamber, that houses the rotation mechanism and the plurality of material sources, is scaled based on the orthogonal distance and the lateral distance in relationship to a radius of the substrate.