Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Abstract: An electronic device includes a substrate, an electronic component, a structure, and an adhesive. The substrate has a proximal surface. The electronic component includes at least one die, wherein the electronic component is attached to the substrate. The structure has a proximal surface adjacent to proximal surface of the substrate. A feature extends from the proximal surface of the structure or the substrate, and the adhesive contacts the feature and the proximal surfaces of the structure and the substrate. In another aspect, a process of forming the electronic device can include applying the adhesive, placing the substrate and structure adjacent to each other, wherein the adhesive contacts the feature and the proximal surfaces of the substrate and the substrate, and curing the adhesive.

Abstract: An electrostatic transducer includes a substrate oriented in a plane, a fixed electrode supported by the substrate, and a moveable electrode supported by the substrate, spaced from the fixed electrode in a first direction parallel to the plane, and configured for movement in a second direction transverse to the plane, such that an extent to which the fixed and moveable electrodes overlap changes during the movement. The fixed and moveable electrodes comprise one or more of a plurality of conductive layers, the plurality of conductive layers including at least three layers. The fixed electrode includes a stacked arrangement of two or more spaced apart conductive layers of the plurality of conductive layers.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by replacing at least the sacrificial material layers with at least one electrically conductive material. Contact via structures are formed through the retro-stepped dielectric material portion on the electrically conductive layers. A first support pillar structure is located directly below a first contact via structure.

Abstract: The embodiment of the present application provides a display panel and a manufacturing method thereof. The display panel comprises a light-emitting device layer, a first optical structure layer, a second optical structure layer and an anti-reflection layer. The light-emitting device layer comprises light-emitting diodes and a retaining wall. The second optical structure layer is filled in the opening areas. Meanwhile, a refractive index of the second optical structure layer is greater than a refractive index of the first optical structure layer. The light extraction rate and display effect are improved with the optical structure layers with different refractive indexes and the retaining wall.

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

Abstract: A structure comprising a nanoparticle converting electromagnetic radiation of a first wavelength into electromagnetic radiation of a second wavelength range, an interlayer at least partially surrounding the nanoparticle, and an encapsulation at least partially surrounding the interlayer is specified, wherein the interlayer comprises a plurality of first amphiphilic ligands and a plurality of second amphiphilic ligands and the first ligands and the second ligands are intercalated. Furthermore, an agglomerate comprising a plurality of structures, an optoelectronic device as well as methods for producing a structure and an agglomerate are disclosed.

Abstract: The present application provides a display panel, a display device, and a manufacturing method of the display panel. The display panel includes a substrate, an insulating layer, and an interlayer dielectric layer that are sequentially stacked. The interlayer dielectric layer includes a first section located in the display area and a second section located in the fan-out area, and a hollowed groove is defined in the second section and filled with an elastic material. Therefore, a bending resistance of film layers in the fan-out area is improved, and a problem that the film layers in the fan-out area is easily broken after bending and binding processes of the display panel is prevented.

Abstract: The disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure. The method for manufacturing the semiconductor structure comprises: a substrate, in which a first protective structure is formed, is provided; a first dielectric layer is formed on the substrate; and a second protective structure is formed in the first dielectric layer and the substrate. A projection of the second protective structure and a projection of the first protective structure in a direction perpendicular to a surface of the substrate are at least partially overlapped, and there is a spacing between a projection of the second protective structure and a projection of the first protective structure in a direction along the surface of the substrate.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main face and a second main face opposite each other; a dielectric film on a part of the first main face, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in an outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion of the dielectric film; a first electrode layer on the electrode layer disposing portion of the dielectric film; and a protective layer continuously covering a range from an end portion of the first electrode layer to the outer peripheral end of the dielectric film.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A display device is provided. The display device includes a substrate, a channel layer, a first metal layer, and a second metal layer. The channel layer is disposed on the substrate and includes a first channel layer and a second channel layer. The first metal layer is disposed on the channel layer and includes a first gate and a second gate. The second metal layer is disposed over the first metal layer and includes a first source, a first drain, and a second source. The first gate, the first source, the first drain, and the first channel layer form a first transistor. The second gate, the second source, the first drain, and the second channel layer form a second transistor. The first transistor and the second transistor are connected in parallel.

Abstract: A display substrate, a method for manufacturing a display substrate and a display device are provided, and the display substrate includes: a base having a first surface, a second surface and a side surface, the base includes a display area and an epitaxial area; a driving functional layer in the display area and first binding electrodes in the epitaxial area on the first surface, the first binding electrodes are coupled with the driving functional layer; second binding electrodes located on the second surface and coupled with the first binding electrodes through side wirings; a portion of each side wiring is located on the side surface; a blocking wall on the first surface and in the epitaxial area, an orthographic projection of the blocking wall on the base at least passes through spacing regions between every two adjacent first binding electrodes along an arrangement direction of the first binding electrodes.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

Abstract: A compound closed-type metal lid for a semiconductor chip package is provided. The compound closed-type metal lid includes a cover plate, and a frame bottom board. The cover plate has a frame body, and a plurality of riveting holes. The riveting holes penetrate through the frame body and are distributed symmetrically on the frame body. The frame bottom board has a frame body, a plurality of riveting protrusions, and an opening. The riveting protrusions are distributed on an upper surface of the frame body. The cover plate is disposed on an upper surface of the frame bottom board. The riveting protrusions are correspondingly riveted in the riveting holes.

Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

Abstract: An array substrate and a manufacturing method thereof, and a display panel are disclosed. The array substrate includes a substrate, a switching transistor, and a driving transistor. The switching transistor and the driving transistor are disposed on the substrate. An orthogonal projection of the switching transistor on the substrate is staggered from an orthogonal projection of the driving transistor on the substrate. A mobility of the switching transistor is greater than a mobility of the driving transistor, and a threshold voltage of the driving transistor is less than a threshold voltage of the switching transistor.

Abstract: A device includes a substrate, a light sensitive element, a pinning region, a lightly-doped region, a floating node, and a gate stack. The light sensitive element is in the substrate. The pinning region is in the substrate and is over the light sensitive element. The lightly-doped region is laterally adjacent the pinning region. The floating node is in the pinning region, the floating node being spaced from and surrounded by the lightly-doped region. A first portion of the pinning region is between the floating node and the lightly-doped region. The gate stack is over the first portion of the pinning region.

Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

Abstract: A method for manufacturing an image display device including providing a plurality of first subpixels and a second subpixel, where the plurality of first subpixels have a plurality of first light-emitting elements and are configured to emit red, green, and blue light, and the second subpixel has a second light-emitting element and being configured to emit blue light. A defective subpixel detection process includes turning on the plurality of first light-emitting elements, and acquiring data of position of at least one defective subpixel among the plurality of first subpixels, where the defective subpixel is supposed to emit predetermined light with a predetermined color. A wavelength conversion layer formation process includes providing a wavelength conversion layer over the second light-emitting element to convert emission light emitted from the second light-emitting element to the predetermined light with the predetermined color if the predetermined color is red or green.