Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.

Abstract: A spin-transfer torque (STT) magnetoresistive memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer having a fixed magnetization direction, a free layer stack, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer stack. The free layer stack has a total thickness of less than 2 nm, and contains in order, a proximal ferromagnetic layer located proximal to the nonmagnetic tunnel barrier layer, a first non-magnetic metal sub-monolayer, an intermediate ferromagnetic layer, a second non-magnetic metal sub-monolayer, and a distal ferromagnetic layer.

Abstract: A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.

Abstract: A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.

Abstract: In embodiments, methods of configuring a molecular beam epitaxy system include providing a rotation mechanism configured to rotate a substrate deposition plane of a substrate around a center axis of the substrate deposition plane. A positioning mechanism is provided, being configured to allow the substrate deposition plane and an exit aperture of at least one material source in a plurality of material sources to be adjusted in position relative to each other between production runs. The at least one material source has a predetermined material ejection spatial distribution with a symmetry axis that intersects the substrate at a point offset from the center axis. A size of a reaction chamber, that houses the rotation mechanism and the plurality of material sources, is scaled based on the orthogonal distance and the lateral distance in relationship to a radius of the substrate.

Abstract: A magnetic memory device includes a first magnetic layer extending in a first direction, a pinned layer on the first magnetic layer, and a second magnetic layer vertically overlapping with the pinned layer with the first magnetic layer interposed between the pinned layer and the second magnetic layer. The first magnetic layer includes, a plurality of magnetic domains arranged in the first direction, and at least one magnetic domain wall between the plurality of magnetic domains, and a magnetization direction of the second magnetic layer is substantially parallel to a top surface of the first magnetic layer.

Abstract: A system including a plurality of cooling cells is described. Each of the cooling cells includes a support structure and a cooling element. The cooling element has a central region having an axis and a perimeter. The cooling element IS supported by the support structure at the central region and along the axis. At least a portion of the perimeter being unpinned. The cooling element is configured to undergo vibrational motion when actuated to drive a fluid toward a heat-generating structure. A portion of the cooling cells aligned along the axis are physically connected such that the cooling cells form an integrated cooling cell tile.

Abstract: The present disclosure provides a novel form of a display device which enables semiconductor light emitting elements having a vertical structure to be assembled onto a substrate and then wiring process to be performed stably without any change to the position of the elements during post-processing.

Abstract: An OLED display device including a display area is provided. A first and second thin film transistors (TFTs) are arranged in the display area, the first TFT includes a first active layer, the second TFT includes a second active layer, a material of the first active layer is different from that of the second active layer. The OLED display device includes a substrate, the second active layer, a second gate of the second TFT, the first active layer, a first gate of the first TFT, a first source and drain of the first TFT, a second source and drain of the second TFT, a first data line in a same layer as the second source and drain, a first planarization layer on the first data line, and a second data line on the first planarization layer and electrically insulated from the first data line.

Abstract: Provided are a display substrate and a display apparatus. The display substrate includes a first display region and a second display region, and a pixel density of the first display region is higher than a pixel density of the second display region. A first pixel circuit of a first sub-pixel in the first display region includes one pixel circuit unit, and a second pixel circuit of a second sub-pixel in the second display region includes two pixel circuit units. The first pixel circuit is configured to be connected with a first power voltage terminal to receive a first power voltage as a pixel power voltage, and the second pixel circuit is configured to be connected with a second power voltage terminal to receive a second power voltage as a pixel power voltage and the first power voltage is different from the second power voltage.

Abstract: A light-emitting substrate and a display device. The light-emitting substrate includes a base substrate, an electrode layer and a definition pattern layer; the electrode layer is at a side of the base substrate, and the definition pattern layer is at a side of the electrode layer away from the base substrate; the electrode layer includes a first electrode, and the definition pattern layer covers at least a part of the first electrode; the definition pattern layer includes a plurality of first openings, the plurality of first openings expose a same first electrode. Therefore, the light-emitting substrate can ensure the bonding success rate of the light-emitting substrate, and thus can further improve the product yield of the light-emitting substrate.

Abstract: The embodiment of the present application discloses a display substrate, a display panel and a manufacturing method of the display substrate. The display substrate comprises a base substrate and a composite structure layer. The composite structure layer comprises a conductive layer and a colloidal medium layer. The colloidal medium layer comprises a plurality of conductive particles. The plurality of conductive particles are located at a position of the colloidal medium layer close to the conductive layer to form a conductive particle part. The present application can reduce the height difference between the conductive layer and the edge of the conductive particle part, and reduce the risk of fracture or breakdown.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivi

Abstract: Thermosetting resin compositions useful for liquid compression molding encapsulation of a reconfigured wafer are provided. The so-encapsulated molded wafer offers improved resistance to warpage, compared to reconfigured wafers encapsulated with known encapsulation materials.

Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

Abstract: The present disclosure provides a light-emitting device. The light-emitting device includes a substrate layer and pixel isolation structures disposed on a first surface of the substrate layer, a plurality of sub-pixel regions isolated from each other are formed between the pixel isolation structures, and the light-emitting device further include a plurality of light-emitting units disposed one-to-one in each of the sub-pixel regions for emitting different wavelengths of light, the light-emitting units being electroluminescent devices, and an initial external quantum efficiency of each of the light-emitting units being different; a plurality of light extraction structures disposed one-to-one in at least part of the plurality of sub-pixel regions for increasing an external quantum efficiency of the corresponding light-emitting unit, reducing deviations of the actual external quantum efficiency of each of the light-emitting units.