Abstract: The embodiment of the present application discloses a display substrate, a display panel and a manufacturing method of the display substrate. The display substrate comprises a base substrate and a composite structure layer. The composite structure layer comprises a conductive layer and a colloidal medium layer. The colloidal medium layer comprises a plurality of conductive particles. The plurality of conductive particles are located at a position of the colloidal medium layer close to the conductive layer to form a conductive particle part. The present application can reduce the height difference between the conductive layer and the edge of the conductive particle part, and reduce the risk of fracture or breakdown.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivi

Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.

Abstract: Thermosetting resin compositions useful for liquid compression molding encapsulation of a reconfigured wafer are provided. The so-encapsulated molded wafer offers improved resistance to warpage, compared to reconfigured wafers encapsulated with known encapsulation materials.

Abstract: The present disclosure provides a light-emitting device. The light-emitting device includes a substrate layer and pixel isolation structures disposed on a first surface of the substrate layer, a plurality of sub-pixel regions isolated from each other are formed between the pixel isolation structures, and the light-emitting device further include a plurality of light-emitting units disposed one-to-one in each of the sub-pixel regions for emitting different wavelengths of light, the light-emitting units being electroluminescent devices, and an initial external quantum efficiency of each of the light-emitting units being different; a plurality of light extraction structures disposed one-to-one in at least part of the plurality of sub-pixel regions for increasing an external quantum efficiency of the corresponding light-emitting unit, reducing deviations of the actual external quantum efficiency of each of the light-emitting units.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. A profile of the first type conductive layer perpendicularly projected on a bottom surface of the second type conductive layer is surrounded by an edge of the second type conductive layer.

Abstract: Embodiments of present invention provide a method of forming a transistor structure. The method includes receiving a first and a second gate region of a first and a second transistor, the second transistor being adjacent to the first transistor; forming a first work-function metal surrounding the first gate region; truncating the first work-function metal at a first boundary between the first transistor and the second transistor; forming one or more work-function metals surrounding the first gate region; truncating the one or more work-function metals at a second boundary between the first boundary and the second transistor; and forming another work-function metal surround the first and second gate regions. A transistor structure formed thereby is also provided.

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness.

Abstract: The present invention provides an infrared photodetection device for detecting infrared radiation with a wavelength of 700 nm or larger comprising: a carrier transfer member comprised of a non-metallic material with a band gap; an absorber on one side of the carrier transfer member, and in electrical contact with the carrier transfer member, the absorber being a metallic material in which electron-hole pairs are excited upon absorption of infrared radiation; and a semiconductor on the other side of the carrier transfer member, and in electrical contact with the carrier transfer member; and wherein the carrier transfer member contains trap states such that majority carriers excited in the absorber due to infrared radiation are conducted via the trap states through the carrier transfer member to be collected b the semiconductor.

Abstract: A manufacturing method of an electronic device is provided by the present disclosure. The method includes: providing a substrate including a non-discarding portion and a discarding portion adjacent to the non-discarding portion; forming a first test wiring extending through the non-discarding portion and the discarding portion; cutting the substrate on a target line, wherein the target line is aligned with a boundary between the non-discarding portion and the discarding portion; performing a first conducting test on the first test wiring; and determining the substrate to be in an off-target cutting state when a result of the first conducting test is a short circuit state, or determining the substrate to be in an on-target cutting state when the result of the first conducting test is an open circuit state.

Abstract: Provided on a substrate 1 are an N+ layer connecting to a source line SL, a first Si pillar as a P+ layer standing in an upright position along the vertical direction, and a second Si pillar as a P layer. An N+ layer connecting to a bit line BL is provided on the second Si pillar. A first gate insulating layer is provided so as to surround the first Si pillar, and a second gate insulating layer is provided so as to surround the second Si pillar. A first gate conductor layer connecting to a plate line PL is provided so as to surround the first insulating layer, and a second gate conductor layer connecting to a word line WL is provided so as to surround the second insulating layer.

Abstract: According to one embodiment, a magnetic memory device includes a memory cell including a magnetoresistance effect element, a switching element, and a resistance element connected in series. The resistance element has an asymmetric current-voltage characteristic, and when data is read from the memory cell, a first voltage in a reverse direction is applied to the resistance element, and a resistance value of the resistance element at a time when the first voltage is applied is greater than a resistance value of the resistance element at a time when a second voltage in a forward direction having an absolute value identical to an absolute value of the first voltage is applied.

Abstract: A transistor device including a layer of AlGaN extending between a source and drain of the device; a GaN channel layer extending under the AlGaN layer; a gate stack including a layer of p-doped gallium nitride; and a layer of p-doped InGaN of at least 5 nm in thickness positioned between the AlGaN layer and the p-doped gallium nitride layer, the InGaN layer having a length greater than a length of the gate stack.

Abstract: A display device includes: a substrate; a semiconductor disposed on the substrate; a first gate insulating layer disposed on the semiconductor; a gate electrode disposed on the first gate insulating layer; a second gate insulating layer disposed on the gate electrode; a first storage electrode disposed on the second gate insulating layer; a first interlayer insulating layer disposed on the first storage electrode, where an opening is defined through the first interlayer insulating layer to surround the semiconductor, the gate electrode and the first storage electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer and disposed in the opening, where the second interlayer insulating layer includes an organic material.

Abstract: An electronic device includes a substrate, an electronic component, a structure, and an adhesive. The substrate has a proximal surface. The electronic component includes at least one die, wherein the electronic component is attached to the substrate. The structure has a proximal surface adjacent to proximal surface of the substrate. A feature extends from the proximal surface of the structure or the substrate, and the adhesive contacts the feature and the proximal surfaces of the structure and the substrate. In another aspect, a process of forming the electronic device can include applying the adhesive, placing the substrate and structure adjacent to each other, wherein the adhesive contacts the feature and the proximal surfaces of the substrate and the substrate, and curing the adhesive.

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Abstract: An electrostatic transducer includes a substrate oriented in a plane, a fixed electrode supported by the substrate, and a moveable electrode supported by the substrate, spaced from the fixed electrode in a first direction parallel to the plane, and configured for movement in a second direction transverse to the plane, such that an extent to which the fixed and moveable electrodes overlap changes during the movement. The fixed and moveable electrodes comprise one or more of a plurality of conductive layers, the plurality of conductive layers including at least three layers. The fixed electrode includes a stacked arrangement of two or more spaced apart conductive layers of the plurality of conductive layers.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by replacing at least the sacrificial material layers with at least one electrically conductive material. Contact via structures are formed through the retro-stepped dielectric material portion on the electrically conductive layers. A first support pillar structure is located directly below a first contact via structure.