Patents Examined by Bo B Jang
  • Patent number: 10804171
    Abstract: Disclosed in the present invention are a sensor packaging structure and a manufacturing method thereof. The sensor packaging structure includes a protection board, a circuit structure and a filling structure. A front surface of the circuit structure is connected to a first surface of the protection board. A second surface of the protection board is used as a sensing function surface. The filling structure is located on the outer periphery of the circuit structure and connected to the first surface of the protection board. The sensor packaging structure of the present invention uses the protection board as a protection layer of the functional circuit, which can effectively protect the functional circuit of the sensor. Meanwhile, the protection board is first connected to the circuit structure in the manufacturing method to avoid tolerance accumulation, increasing the manufacturing accuracy of the protection layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 13, 2020
    Assignee: MICROARRAY MICROELECTRONICS CORP., LTD.
    Inventors: Yangyuan Li, Shaobo Ding
  • Patent number: 10804227
    Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Adel A. Elsherbini, Sasha N. Oster
  • Patent number: 10804370
    Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10790293
    Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 29, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 10790147
    Abstract: A method of manufacturing a semiconductor device includes forming an etch target layer on a substrate; forming an amorphous metal layer on the etch target layer, the amorphous metal layer comprising nitrogen between 15 atomic percentage (at %) and 25 at %; forming an amorphous metal hardmask by patterning the amorphous metal layer; and etching the etch target layer by using the amorphous metal hardmask as an etching mask.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Hee Lee, Se-Ran Oh, Hyun-Su Kim, Ik-Soo Kim, Seong-Gil Park, Geun-O Jeong
  • Patent number: 10784149
    Abstract: The present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (BEOL) layer, an epitaxial layer over the BEOL layer, and a buried oxide (BOX) layer with discrete holes over the epitaxial layer. The epitaxial layer includes an air-cavity, a first device section, and a second device section. Herein, the air-cavity is in between the first device section and the second device section and directly in connection with each discrete hole in the BOX layer. The mold compound resides directly over at least a portion of the BOX layer, within which the discrete holes are located. The mold compound does not enter into the air-cavity through the discrete holes.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10773952
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
  • Patent number: 10777265
    Abstract: An integrated circuit includes transistor devices, each having a back gate. A controller is connected to the back gate to apply voltages to the back gate, wherein a first mode includes a first voltage for operational threshold voltages for the transistor devices, and a second mode includes a second voltage that enhances threshold voltage variability of the plurality of transistor devices to provide a physically unclonable function (PUF) for chip identification.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10770362
    Abstract: Methods and systems for determining band structure characteristics of high-k dielectric films deposited over a substrate based on spectral response data are presented. High throughput spectrometers are utilized to quickly measure semiconductor wafers early in the manufacturing process. Optical models of semiconductor structures capable of accurate characterization of defects in high-K dielectric layers and embedded nanostructures are presented. In one example, the optical dispersion model includes a continuous Cody-Lorentz model having continuous first derivatives that is sensitive to a band gap of a layer of the unfinished, multi-layer semiconductor wafer. These models quickly and accurately represent experimental results in a physically meaningful manner. The model parameter values can be subsequently used to gain insight and control over a manufacturing process.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 8, 2020
    Assignee: KLA Corporation
    Inventors: Natalia Malkova, Leonid Poslavsky, Ming Di, Qiang Zhao, Dawei Hu
  • Patent number: 10768138
    Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: IMEC VZW
    Inventors: Koen Martens, Nadine Collaert, Eddy Kunnen, Simone Severi
  • Patent number: 10770691
    Abstract: A method for producing an organic EL device having an anode, a cathode, at least one organic functional layer disposed between the anode and the cathode, and a sealing layer, comprising a step of forming the anode, a step of forming the cathode, a step of forming the at least one organic functional layer and a step of forming the sealing layer, wherein the average concentration: A (ppm) of ammonia to which the organic EL device during production is exposed from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer and the exposure time thereof: B (sec) satisfy the formula (1-1): 0?A×B?105??(1-1).
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 8, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masataka Iwasaki, Takaaki Okamoto
  • Patent number: 10763130
    Abstract: Systems and methods are provided for producing an integrated circuit package, e.g., an SOIC package, having reduced or eliminated lead delamination caused by epoxy outgassing resulting from the die attach process in which an integrated circuit die is attached to a lead frame by an epoxy. The epoxy outgassing may be reduced by heating the epoxy during or otherwise in association with the die attach process, e.g. using a heating device provided at the die attach unit. Heating the epoxy may achieve additional cross-linking in the epoxy reaction, which may thereby reduce outgassing from the epoxy, which may in turn reduce or eliminate subsequent lead delamination. A heating device located at or near the die attach site may be used to heat the epoxy to a temperature of 55° C.±5° C. during or otherwise in association with the die attach process.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 1, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Taweesak Laevohan, Philbert Reyes, Jaggrit Vilairat, Sutee Thanaisawn, Janpen Phimphuang, Somsak Chunpangam
  • Patent number: 10763242
    Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Son, Jung-Hwan Choi, Seok-Hun Hyun
  • Patent number: 10734547
    Abstract: An embodiment relates to a semiconductor device, a semiconductor device package, and a method for producing a semiconductor device, the semiconductor device comprising a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and an intermediate layer disposed between the first conductivity type semiconductor layer and the active layer, or disposed inside the first conductivity type semiconductor layer, wherein the first conductivity type semiconductor layer, the intermediate layer, the active layer, and the second conductivity type semiconductor layer include aluminum, and the intermediate layer includes a first intermediate layer having a lower aluminum composition than that of the first conductivity type semiconductor layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Rak Jun Choi, Byeoung Jo Kim, Hyun Jee Oh, Jung Yeop Hong
  • Patent number: 10731274
    Abstract: A group III nitride laminate having monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and an electrode is provided. The group III nitride laminate is characterized in that an n-type contact layer made of (AlYGa1-Y)2O3 (0.0?Y<0.3) is provided between the monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and the electrode. Furthermore, a vertical semiconductor device including the above-described group III nitride laminate is provided.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 4, 2020
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Yoshinao Kumagai, Hisashi Murakami, Toru Kinoshita
  • Patent number: 10714453
    Abstract: A semiconductor package includes a first semiconductor chip disposed on a substrate. A first upward pad is disposed on an upper surface of the first semiconductor chip. A second semiconductor chip is arranged with an offset above the first semiconductor chip. A first downward pad is disposed on a lower surface of the second semiconductor chip. A first bonding wire connects the first upward pad and the substrate. A first inter-chip connector is interposed between the first upward pad and the first downward pad. A side surface of the second semiconductor chip is arranged above the first upward pad.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo Jin Kim, Young Sik Kim
  • Patent number: 10699948
    Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 30, 2020
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Jan Kubik, Bernard P. Stenson, Michael Noel Morrissey
  • Patent number: 10700084
    Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hoon Kim, Hong-Soo Kim, Ju-Yeon Lee
  • Patent number: 10693033
    Abstract: A semiconductor chip (100) is provided, having a first semiconductor layer (1), which has a lateral variation of a material composition along at least one direction of extent. Additionally provided is a method for producing a semiconductor chip (100).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 23, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Alfred Lell, Andreas Löffler, Christoph Eichler, Bernhard Stojetz, André Somers
  • Patent number: 10685965
    Abstract: A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li