Patents Examined by Bo B Jang
  • Patent number: 10615321
    Abstract: A light emitting diode package includes: at least one light emitting diode chip; a housing on which the at least one light emitting diode chip is mounted, the housing being open at at least one surface thereof to allow light emitted from the at least one light emitting diode chip to be discharged through the open surface of the housing; and a plurality of pads disposed on a second surface of the housing different from a first surface of the housing through which light is discharged, the plurality of pads being electrically connected to the at least one light emitting diode chip, wherein the housing has a plurality of grooves formed on a third surface thereof adjacent to the second surface.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 7, 2020
    Assignee: SEOUL SEMICONDUCTOR CO., LTD.
    Inventors: Seung Ri Choi, Hyuck Jun Kim, Se Min Bang, Do Choul Woo, Se Won Tae
  • Patent number: 10589993
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 17, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
  • Patent number: 10590306
    Abstract: A resin composition for a display substrate, the resin composition including a solvent and a heat-resistant resin or a precursor thereof, wherein the solvent has as a main component an amide compound having a surface tension of 35 mN/m or less at 25° C. Provided is a resin composition for a display substrate, whereby pinholing of a thin film is not prone to occur.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 17, 2020
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Tomoki Ashibe, Daichi Miyazaki, Koji Ueoka, Akinori Saeki, Masahito Nishiyama
  • Patent number: 10585349
    Abstract: According to one embodiment, an imprint apparatus includes: an ejection unit that ejects droplets of a resin-based mask material on a substrate on the basis of a droplet dropping condition; and a control unit that selects a first droplet dropping condition according to a pattern to be transferred to the resin-based mask material and a second droplet dropping condition according to an underlying step difference amount that is concave-convex of a first shot area and causes the ejection unit to eject the droplets with respect to the first shot area, wherein the shot area where a pattern is formed on the substrate by one time of imprinting is set.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Satoshi Usui
  • Patent number: 10586843
    Abstract: A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Wei Wang, Zheng Xu
  • Patent number: 10573518
    Abstract: A method of performing a film formation on target substrates in a state where a substrate holder for holding the target substrates in a shelf shape is loaded into a vertical reaction container from a lower opening thereof and the lower opening is closed by a lid. The method includes: performing the film formation on the target substrates by supplying a processing gas into the reaction container; opening the lid and unloading the substrate holder from the reaction container; performing the film formation on a bottom portion of the reaction container including an inner surface of the lid by closing the lower opening with the lid and supplying a coating gas different from the processing gas into the reaction container; and performing the film formation on the target substrates by opening the lid, loading the substrate holder into the reaction container, and supplying the processing gas into the reaction container.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yoshikazu Furusawa
  • Patent number: 10566185
    Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 18, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Han Wang, Qi Xie, Delphine Longrie, Jan Willem Maes, David de Roest, Julian Hsieh, Chiyu Zhu, Timo Asikainen
  • Patent number: 10566424
    Abstract: A method of manufacturing a silicon wafer is provided that includes extracting an n-type silicon ingot over an extraction time period from the a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, thereby compensating an n-type doping in the n-type silicon ingot by 10% to 80%; slicing the silicon ingot; forming hydrogen related donors in the silicon wafer by irradiating the silicon wafer with protons; and annealing the silicon wafer subsequent to the forming of the hydrogen related donors in the silicon wafer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Nico Caspary, Helmut Oefner, Hans-Joachim Schulze
  • Patent number: 10559683
    Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros
  • Patent number: 10559714
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Patent number: 10559468
    Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon carbonitride material, silicon oxycarbide material, silicon carbon-oxynitride, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 11, 2020
    Assignee: Lam Research Corporation
    Inventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
  • Patent number: 10553787
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: February 4, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Michael Pinarbasi, Michail Tzoufras, Bartlomiej Adam Kardasz
  • Patent number: 10554015
    Abstract: A method of making a quasi-phase-matching (QPM) structure comprising the steps of: applying a pattern to a substrate to define a plurality of growth regions and a plurality of voids; growing in a growth chamber a crystalline inorganic material on only the growth regions in the pattern, the crystalline inorganic material having a first polarity; applying an electric field within the growth chamber containing the patterned substrate with the crystalline inorganic material, wherein the electric field reaches throughout the growth chamber; and growing a crystalline organic material having a second polarity in the voids formed in the inorganic material under the influence of the electric field to influence the magnitude and the direction of the second polarity of the crystalline organic material, wherein the second polarity of the crystalline organic material is influenced to be different from the first polarity of the crystalline inorganic material in magnitude and/or direction.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: February 4, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventor: Vladimir Tassev
  • Patent number: 10554010
    Abstract: A method of producing a semiconductor laser device includes the steps of preparing first and second substrate products each of which includes a substrate and a stacked semiconductor layer formed on the substrate, the first and second substrate products being different from each other; etching the first substrate product with a chlorine-based gas in a vacuum chamber by using a dry etching method; evacuating the vacuum chamber while monitoring the pressure of hydrogen chloride in the vacuum chamber so as to obtain a partial pressure of the hydrogen chloride within a predetermined range; after evacuating the vacuum chamber, introducing the second substrate product into the vacuum chamber while maintaining a vacuum state inside the vacuum chamber; and etching the second substrate product with a chlorine-based gas in the vacuum chamber by using the dry etching method.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 4, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yukihiro Tsuji
  • Patent number: 10553552
    Abstract: To provide a wafer laminate which permits easy bonding between a support and a wafer, permits easy delamination of a wafer from a support, enables enhanced productivity of a thin wafer, and is suited to production of a thin wafer, and for a method of producing the wafer laminate. The wafer laminate includes a support, an adhesive layer formed on the support, and a wafer laminated in such a manner that its front surface having a circuit surface faces the adhesive layer. The adhesive layer includes a light-shielding resin layer A and a non-silicone thermoplastic resin-coating resin layer B in this order from the support side. The resin layer A is composed of a resin that contains a repeating unit having a condensed ring, and the resin layer B has a storage elastic modulus E? at 25° C. of 1 to 500 MPa and a tensile break strength of 5 to 50 MPa.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 4, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Hideto Kato
  • Patent number: 10549988
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
  • Patent number: 10553482
    Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 4, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Han Wang, Qi Xie, Delphine Longrie, Jan Willem Maes, David de Roest, Julian Hsieh, Chiyu Zhu, Timo Asikainen, Krzysztof Kachel, Harald Profijt
  • Patent number: 10546941
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10532374
    Abstract: A thin film production method according to one embodiment includes: a coating film forming step of forming a coating film by discharging a coating liquid on a support from first to M-th line heads (M is 2 or larger and N or smaller) while allowing the support to pass through N line heads once; and a drying step of obtaining a thin film by drying the coating film. A thin film forming nozzle hole 28 of the m-th line head (m is 2 or larger and M or smaller) is arranged to be positioned between adjacent thin film forming nozzle holes in an (m?1)-th thin film forming nozzle hole array Qm-1. Every time the first line head discharges the coating liquid, the m-th line head applies the coating liquid onto the support at a predetermined delay time with respect to a discharge time of the first line head. The first to M-th line heads discharge the coating liquid from the film forming nozzle hole selected in accordance with a shape of a thin film formation region onto the support.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 14, 2020
    Assignee: SUMITOMO CHEMICAL CO., LTD.
    Inventors: Motoo Noda, Hidekazu Shiomi, Akihide Suzuki
  • Patent number: 10529891
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana