Patents Examined by Bo B Jang
  • Patent number: 10411046
    Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jee Hoon Kim, Shin Hyuk Yang, Yong Hoon Won, Kwang Soo Lee
  • Patent number: 10410935
    Abstract: Methods and systems for determining band structure characteristics of high-k dielectric films deposited over a substrate based on spectral response data are presented. High throughput spectrometers are utilized to quickly measure semiconductor wafers early in the manufacturing process. Optical models of semiconductor structures capable of accurate characterization of defects in high-K dielectric layers and embedded nanostructures are presented. In one example, the optical dispersion model includes a continuous Cody-Lorentz model having continuous first derivatives that is sensitive to a band gap of a layer of the unfinished, multi-layer semiconductor wafer. These models quickly and accurately represent experimental results in a physically meaningful manner. The model parameter values can be subsequently used to gain insight and control over a manufacturing process.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 10, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Natalia Malkova, Leonid Poslavsky, Ming Di, Qiang Zhao, Dawei Hu
  • Patent number: 10403504
    Abstract: A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: September 3, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Delphine Longrie, David Kurt de Roest
  • Patent number: 10392725
    Abstract: A method for depositing silicon feedstock material may include introducing a first gas including silicon into a reactor chamber and introducing a second gas including at least one of gallium or indium into the reactor chamber and depositing silicon doped with at least one of gallium or indium onto a surface within the reactor chamber. Doped silicon feedstock material may be obtained by the method may be used for obtaining a silicon wafer, a solar cell, and/or a PV module.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 27, 2019
    Inventor: Frank Asbeck
  • Patent number: 10388737
    Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 20, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Patent number: 10388902
    Abstract: A device includes a first light-emitting device and a second light-emitting device, each including an anode, a cathode, charge transport layers disposed between the anode and the cathode, and an emissive layer disposed between the charge transport layers. For the first light-emitting device, the emissive layer includes first quantum dots, the emissive layer configured to emit light at a first wavelength. For the second light-emitting device, the emissive layer includes emissive sub-layers provided in a stacked arrangement in a thickness direction. A first one of the emissive sub-layers includes the first quantum dots and is configured to emit light at the first wavelength, and a second one of the emissive sub-layers includes second quantum dots and is configured to emit light at a second wavelength different than the first wavelength.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: August 20, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventors: James Andrew Robert Palles-Dimmock, Edward Andrew Boardman, Tim Michael Smeeton, Enrico Angioni
  • Patent number: 10388621
    Abstract: A method of making nanoscale devices, the method including: depositing a metal film on a surface of a first substrate; annealing the metal film to form a plurality of metal island structures on the surface of the first substrate; laying metal nanospheres on the surface of the first substrate; baking the first composite structure to make the metal nanospheres become a plurality of metal crystalline balls; forming a photoresist layer on the first surface of the second composite structure; placing a release agent layer on a second substrate, applying an external force to press the photoresist layer on the release agent layer under an inert atmosphere; heating the second composite structure, the photoresist layer, the release agent layer, and the second substrate are and applying voltages in three stages.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 20, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10388823
    Abstract: A semiconductor chip (100) is provided, having a first semiconductor layer (1), which has a lateral variation of a material composition along at least one direction of extent. Additionally provided is a method for producing a semiconductor chip (100).
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: August 20, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Alfred Lell, Andreas Loeffler, Christoph Eichler, Bernhard Stojetz, Andre Somers
  • Patent number: 10388527
    Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 20, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Norihiro Togawa, Narumasa Soejima, Shoji Mizuno
  • Patent number: 10381261
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew Marquis Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Patent number: 10381291
    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Brandon M. Rawlings, Aleksandar Aleksov, Feras Eid, Javier Soto
  • Patent number: 10381430
    Abstract: A structure with an interconnection layer for redistribution of electrical connections includes a plurality of first electrical connections disposed on a substrate in a first arrangement. An insulating layer is disposed on the substrate over the first electrical connections. A plurality of second electrical connections is disposed on the insulating layer on a side of the insulating layer opposite the plurality of first electrical connections in a second arrangement. Each second electrical connection is electrically connected to a respective first electrical connection. An integrated circuit is disposed on the substrate and is electrically connected to the first electrical connections. The first electrical connections in the first arrangement have a greater spatial density than the second electrical connections in the second arrangement.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 13, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, Ronald S. Cok
  • Patent number: 10381260
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Inc.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Patent number: 10381537
    Abstract: A light-emitting element disclosed according to an embodiment may comprise: a substrate comprising a body, a plurality of lead electrodes arranged over the body in a first axial direction, and a heat-radiating frame and a plurality of lead frames arranged below the body in a second axial direction; and a light-emitting chip arranged on a first lead electrode, which is arranged in the central area of the body among the plurality of lead electrodes, and electrically connected with the plurality of lead electrodes. The plurality of lead electrodes have a large length in the second axial direction, the heat-radiating frame is arranged in the central area below the body, and the heat-radiating frame and the plurality of lead frames have a large length in the first axial direction and may vertically overlap with the plurality of lead electrodes.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 13, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Hyoung Seok Do, Hwan Hee Jeong, Chong Wook Cho
  • Patent number: 10373827
    Abstract: A method of pattern transfer is provided, comprising: providing a target layer; forming a first pattern above the target layer; forming a second pattern (such as spacer loops) above the target layer and above the first pattern, wherein one closed end of the second pattern partially overlaps with the first pattern; and transferring the second pattern to the target layer, wherein the first pattern stops transferring pattern of the closed end of the second pattern to the target layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10373879
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
  • Patent number: 10366956
    Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
  • Patent number: 10364314
    Abstract: A compound or a resin represented by the following formula (1).
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 30, 2019
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kana Okada, Junya Horiuchi, Takashi Makinoshima, Masatoshi Echigo
  • Patent number: 10359701
    Abstract: A material for forming an underlayer film for lithography, in which a compound represented by the following formula (0) is used.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: July 23, 2019
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kana Okada, Takashi Makinoshima, Masatoshi Echigo, Go Higashihara, Atsushi Okoshi
  • Patent number: 10325933
    Abstract: The present disclosure provides an array substrate comprising a plurality of gate lines, and a plurality of data lines that intersect the plurality of gate lines. A plurality of pixel units are defined by the plurality of gate lines and the plurality of data lines which intersect each other. Each pixel unit comprises a thin film transistor, a gate insulating layer, a passivation layer arranged on one side of the gate insulating layer, a pixel electrode and a common electrode, wherein a source and a drain of the thin film transistor are arranged between the passivation layer and the gate insulating layer, the common electrode is arranged on the other side of the gate insulating layer opposite to the passivation layer, and the pixel electrode is arranged on the passivation layer. The present disclosure further provides a method for manufacturing an array substrate and a display device.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 18, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yunyun Tian, Hyunsic Choi, Yoonsung Um