Abstract: An oxide thin film transistor includes an oxide active layer, a first loose layer and a first oxygen release layer. The first loose layer is at least disposed on a first surface of the oxide active layer perpendicular to a thickness direction of the oxide active layer, and is in contact with the oxide active layer. A material of the first loose layer includes a first inorganic oxide insulating material. The first oxygen release layer is disposed on a surface of the first loose layer facing away from the oxide active layer, and is in contact with the first loose layer. A material of the first oxygen release layer is a first oxygen-containing insulating material.

Abstract: A device is disclosed. The device includes a housing that defines a chamber. The chamber is to be at least partially filled with an electrolyte material. The device also includes a plurality of electrodes that are at least partially embedded in the housing and exposed to the chamber. The device further includes an access port that provides fluid communication between an interior of the housing and the outside environs.

Abstract: A method of manufacturing an optoelectronic device, including the steps of: forming, on a first surface of a first including assemblies of electronic components, a stack of insulating layers and of conductive tracks; forming, on another wafer, light-emitting diodes each comprising ends; forming a metal layer on at least a portion of the surface of the first wafer and another metal layer on at least a portion of the surface of the second wafer, the other metal layer being electrically coupled to the end of each light-emitting diode; placing into contact the metal layers; forming an insulated conductive via connecting another surface of the wafer to a conductive track; and forming insulated conductive trenches surrounding diodes.

Abstract: A display panel, a preparation method thereof, and a display device are disclosed. The display panel includes: a plurality of pixel units arranged in an array; a plurality of first signal lines extending in a first direction and arranged in a second direction; and a plurality of first connecting electrodes arranged in the second direction; where the first direction intersects with the second direction. The plurality of pixel units form m pixel rows arranged in sequence along the first direction and each extending along the second direction, where m is an integer greater than 1; and a projection of at least one pixel unit in an m-th pixel row on a plane perpendicular to the second direction and projections of the first connecting electrodes on the plane perpendicular to the second direction have an overlapped area.

Abstract: A pixel according to an embodiment of the present disclosure includes a circuit element on a base layer, a protective layer on the circuit element, a first electrode and a second electrode opposite each other on the protective layer, a first insulating layer on the first electrode and the second electrode, a light-emitting element on the first insulating layer at an area between the first electrode and the second electrode, a first contact electrode on a first end of the light-emitting element to connect the first end of the light-emitting element to the first electrode, a second contact electrode on a second end of the light-emitting element to connect the second end of the light-emitting element to the second electrode, and a cavity in the protective layer and the first insulating layer below the light-emitting element corresponding to the area between the first electrode and the second electrode.

Abstract: An array substrate and a display panel are provided. The array substrate includes a data line, a thin film transistor having a gate and a source, a source wire, and a scan line. The source wire includes a predetermined breaking part configured to be cut off to break an electrical connection between the source and the data line. The scan line and the predetermined breaking part have a first predetermined distance in-between, and the first predetermined distance is used to prevent the scan line and the data line from forming a short circuit when a fixing operation is being performed.

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

Abstract: Embodiments include a device having a micro-LED that includes at least two, individually addressable light emitting diodes on a same substrate; a phosphor converter layer disposed on the micro-LED, the phosphor converter layer including phosphor particles having a D50 of greater than 1 ?m and less than 10 ?m.

Abstract: An optical component package includes a main substrate including a plurality of metal bodies, and a vertical insulation part provided between the metal bodies; a cavity provided in an upper surface of the main substrate; a sub-substrate provided in the cavity of the main substrate, the sub-substrate including an insulating body, a plurality of via holes vertically passing through the insulating body and filled with a metal material being electrically connected to each of the metal bodies, and a plurality of metal pads mounted on the insulating body and electrically connected to the plurality of via holes; a plurality of optical components mounted on the plurality of metal pads and electrically connected to the plurality of metal pads; and a light transmitting member provided above the main substrate.

Abstract: A packaging fill material for electrical packaging includes a base material, and a plurality of frangible capsules distributed in the base material. Each frangible capsule includes a liquid penetrant contrast agent therein having a different radiopacity than the base material. In response to a crack forming in the packaging fill material, at least one of the plurality of frangible capsules opens, releasing the liquid penetrant contrast agent into the crack. Cracks can be more readily identified in an IC package including the packaging fill material. The liquid penetrant contrast agent may have a radiopacity that is higher than the base material. Inspection can be carried out using electromagnetic analysis using visual inspection or digital analysis of the results to more easily identify cracks.

Abstract: An emitting device comprising a first light emitter adapted to emit a first radiation, and a second light emitter adapted to emit a second radiation different from the first radiation, the first light emitter comprising a first semiconducting structure and a first radiation converter, the second light emitter comprising a second semiconducting structure and a second radiation converter, each semiconducting structure comprising a semiconducting layer adapted to emit a third radiation, each radiation converter comprising a set of particles able to convert the third radiation into the first or second radiation, the particles of the first radiation converter being attached to a surface by a bulk of photosensitive resin and the particles of the second radiation converter being attached to a surface by grafting.

Abstract: A downconverter layer transfer device, and methods of making and using the downconverter layer transfer device, are disclosed. A downconverter layer transfer device includes a release liner and a downconverter layer disposed on the release liner, the downconverter layer including a downconverter material dispersed throughout an adhesive, the downconverter layer being solid and non-adhesive at a first temperature, and adhesive at an elevated temperature above the first temperature.

Abstract: A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer.

Abstract: A method of forming a multitude of vertical NAND memory cells, includes, in part, forming a multitude of insulating materials on a silicon substrate, forming a trench in the insulating materials to expose a surface of the silicon substrate, depositing a layer of polysilicon along the sidewalls of the trench, filling the trench with oxide, forming a metal layer above the trench, and forming a mono-crystalline channel for the NAND memory cells by applying a voltage between the silicon substrate and the metal layer to cause the polysilicon sidewalls to melt. The melted polysilicon sidewalls is enable to recrystallize into the mono-crystalline channel.

Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.

Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a carboxylic acid is exposed to a substrate to selectively form a blocking layer. In some embodiments, a hydrazide is exposed to a substrate to selectively form a blocking layer. In some embodiments, an alkyl phosphonic acid is exposed to a substrate to selectively form a blocking layer. In some embodiments, the alkyl phosphonic acid is formed in-situ and exposed to the substrate. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed.

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Abstract: An indirect heating method using a laser according to an aspect of the present disclosure includes: a first process of adjacently placing a first material structure containing metal and a second material structure containing inorganic material; and a second process of directly heating the first material structure to indirectly heat the second material structure adjacent to the first material structure by radiating a laser to the first material structure.

Abstract: A capacitor, an array substrate and a method for manufacturing the same, and a display panel are provided. The capacitor includes a main body including a first pole plate and a second pole plate disposed opposite to each other, and the capacitor further includes at least one auxiliary body. Any one of the at least one auxiliary body includes a third pole plate and a fourth pole plate disposed opposite to each other, and neither the third pole plate nor the fourth pole plate extends in a plane where the first pole plate is located or a plane where the second pole plate is located. The main body is connected in parallel with the at least one auxiliary body. The array substrate includes a transistor and the capacitor provided by the present disclosure, and the transistor is electrically connected to the capacitor.