Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: depositing a transition metal dichalcogenide thin film on a substrate; and heat-treating the deposited transition metal dichalcogenide thin film.

Abstract: A substrate and a display panel using the substrate are disclosed. The substrate includes a base layer; a magnetic material layer on a side of the base layer; and a thin film transistor (TFT) array layer on a side of the magnetic material layer away from the base layer.

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

Abstract: A first conversion layer material is formed on unmasked pixel areas of a substrate. Mask material is selectively removed from a second set of pixel areas, leaving a third set of pixel areas masked. A coating is formed on sidewalls of the second pixel areas, and then a second conversion layer material is formed on the second pixel areas and against their sidewalls. Mask material is removed from the third pixel areas, a coating is formed on sidewalls of the third pixel areas, and a third conversion layer material is formed on the third pixel areas and against their sidewalls. The resulting wavelength-conversion layer includes contiguously arranged regions of the first, second, and third conversion layer materials, at least two of which are wavelength-converting phosphor materials. The sidewall coatings between the regions act as barriers to lateral light transmission.

Abstract: A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide.

Abstract: A display panel including a wavelength conversion structure that includes a base structure including partition walls that define a first space and a second space, a first quantum dot composite disposed in the first space, and a second quantum dot composite disposed in the second space. The height of the partition wall is greater than or equal to about 5 micrometers and less than or equal to about 50 micrometers, and the first quantum dot composite provides a first top surface and the second quantum dot composite provides a second top surface. A production method for making the wavelength conversion structure uses a first ink composition that includes first quantum dots and a first matrix, and a second ink composition that includes second quantum dots and a second matrix.

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

Abstract: A semiconductor device package includes a leadless leadframe, and a plurality of terminal pads extending to a periphery of the leadframe. At least two of the plurality of terminal pads are interior extending terminal pads that include an interior portion having a shape including at least one curved portion and an exterior portion that extends to the periphery of the leadframe. An integrated circuit (IC) die having at least a semiconductor surface includes circuitry configured for at least one function having nodes connected to bond pads on the leadframe. There is a bonding arrangement between the plurality of terminal pads and the bond pads. A mold compound is for encapsulation of the semiconductor device package.

Abstract: A display device includes a base layer including a display area and a non-display area; and pixels disposed in the display area, each of the pixels including sub-pixels. Each of the sub-pixels includes a pixel circuit layer and a display element layer disposed on the pixel circuit layer. The display element layer includes a partition wall disposed in each of the sub-pixels; a bank disposed between adjacent ones of the sub-pixels; a first electrode and a second electrode disposed on the partition wall and spaced apart from each other; a reflective pattern disposed on the bank; and at least one light emitting element disposed between the first electrode and the second electrode.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

Abstract: An array substrate and a display device are provided. A functional layer of the array substrate is provided with a first opening in a bending region. A filling layer covering the functional layer fills the first opening and provides a second opening at a position of the first opening. A metal layer of the array substrate includes a plurality of metal traces, and the metal traces are bent toward an inside of the second opening in a region overlapping with the second opening.

Abstract: An epitaxial semiconductor structure including a substrate, a semiconductor layer, and a balance structure is provided. The substrate has a first surface and a second surface opposite to each other. The semiconductor layer is formed on the first surface. The balance structure is formed on the second surface, the balance structure is configured to balance the thermal stress on the substrate, and the balance structure is composed of a plurality of non-continuous particulate materials. An epitaxial substrate is also provided.

Abstract: A display substrate, a method for manufacturing the display substrate and a display device are provided. The display substrate includes an Electric Test (ET) region. At least one testing pad and an insulation structure surrounding the testing pad are arranged in the ET region, and a distance between a surface of the insulation structure distal to a base substrate of the display substrate and the base substrate is not greater than a distance between a surface of the testing pad distal to the base substrate and the base substrate.

Abstract: A display panel includes a drive element, a first heat dissipation layer, a light-emitting element, and a second heat dissipation layer. The drive element is disposed on a substrate. The first heat dissipation layer is disposed on the drive element. The light-emitting element is disposed on the first heat dissipation layer and electrically connected to the drive element. The second heat dissipation layer covers the light-emitting element. A refractive index of the first heat dissipation layer is greater than a refractive index of the second heat dissipation layer when a light-emitting surface of the light-emitting element faces the first heat dissipation layer, and the refractive index of the second heat dissipation layer is greater than the refractive index of the first heat dissipation layer when the light-emitting surface of the light-emitting element faces the second heat dissipation layer.

Abstract: A display device includes: a substrate including a pixel area; and a pixel in the pixel area, the pixel including a first sub-light emitting area, a second sub-light emitting area, and a peripheral area surrounding the first and second sub-light emitting areas. The pixel may include: a first electrode, a second electrode, a third electrode, and a fourth electrode that are spaced from each other; a plurality of light emitting elements in the first and second sub-light emitting areas; a bank in the peripheral area and including a first opening corresponding to the first sub-light emitting area and a second opening corresponding to the second sub-light emitting area; and an intermediate bank between the first sub-light emitting area and the second sub-light emitting area and partially overlapping the second and third electrodes in a plan view.

Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.

Abstract: Provided are a display substrate motherboard and manufacturing method thereof, a display substrate and a display apparatus. The display substrate motherboard includes a substrate, a display substrate area on the substrate, and a mark area on the periphery of the display substrate area. The display substrate motherboard also includes a thin film transistor disposed in the display substrate area, a mark structure disposed in the mark area and a planarization layer disposed on one side of the thin film transistor away from the substrate, and the planarization layer includes a groove which is disposed at the corresponding position of the mark structure and extends along a direction close to the substrate, and an orthographic projection of the groove on the substrate covers an orthographic projection of the mark structure on the substrate.

Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.