Patents Examined by Bo B Jang
  • Patent number: 10734547
    Abstract: An embodiment relates to a semiconductor device, a semiconductor device package, and a method for producing a semiconductor device, the semiconductor device comprising a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and an intermediate layer disposed between the first conductivity type semiconductor layer and the active layer, or disposed inside the first conductivity type semiconductor layer, wherein the first conductivity type semiconductor layer, the intermediate layer, the active layer, and the second conductivity type semiconductor layer include aluminum, and the intermediate layer includes a first intermediate layer having a lower aluminum composition than that of the first conductivity type semiconductor layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Rak Jun Choi, Byeoung Jo Kim, Hyun Jee Oh, Jung Yeop Hong
  • Patent number: 10731274
    Abstract: A group III nitride laminate having monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and an electrode is provided. The group III nitride laminate is characterized in that an n-type contact layer made of (AlYGa1-Y)2O3 (0.0?Y<0.3) is provided between the monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and the electrode. Furthermore, a vertical semiconductor device including the above-described group III nitride laminate is provided.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 4, 2020
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Yoshinao Kumagai, Hisashi Murakami, Toru Kinoshita
  • Patent number: 10714453
    Abstract: A semiconductor package includes a first semiconductor chip disposed on a substrate. A first upward pad is disposed on an upper surface of the first semiconductor chip. A second semiconductor chip is arranged with an offset above the first semiconductor chip. A first downward pad is disposed on a lower surface of the second semiconductor chip. A first bonding wire connects the first upward pad and the substrate. A first inter-chip connector is interposed between the first upward pad and the first downward pad. A side surface of the second semiconductor chip is arranged above the first upward pad.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo Jin Kim, Young Sik Kim
  • Patent number: 10699948
    Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 30, 2020
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Jan Kubik, Bernard P. Stenson, Michael Noel Morrissey
  • Patent number: 10700084
    Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hoon Kim, Hong-Soo Kim, Ju-Yeon Lee
  • Patent number: 10693033
    Abstract: A semiconductor chip (100) is provided, having a first semiconductor layer (1), which has a lateral variation of a material composition along at least one direction of extent. Additionally provided is a method for producing a semiconductor chip (100).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 23, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Alfred Lell, Andreas Löffler, Christoph Eichler, Bernhard Stojetz, André Somers
  • Patent number: 10685965
    Abstract: A semiconductor structure, a method for fabricating the semiconductor structure, and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The method also includes forming a gate structure across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin. Further, the method includes forming pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions is formed by performing an ion-doped non-epitaxial layer process on the fin.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10676348
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 9, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
  • Patent number: 10680116
    Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 10672606
    Abstract: A method of forming a coating film includes horizontally supporting a substrate, supplying a coating solution to a central portion of the substrate and spreading the coating solution by a centrifugal force by rotating the substrate at a first rotational speed, decreasing a speed of the substrate from the first rotational speed toward a second rotational speed and rotating the substrate at the second rotational speed to make a surface of a liquid film of the coating solution even, supplying a gas to a surface of the substrate when the substrate is rotated at the second rotational speed to reduce fluidity of the coating solution, and drying the surface of the substrate by rotating the substrate at a third rotational speed faster than the second rotational speed.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kousuke Yoshihara, Takafumi Niwa
  • Patent number: 10665778
    Abstract: Methods and apparatuses for producing magneto resistive apparatuses are provided. Here, structures are formed for defining regions of the same magnetization, magnets are magnetized, and structures are formed within the magnets of the regions, for example, in order to define magneto resistive elements.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Raberg
  • Patent number: 10662375
    Abstract: A method for producing a nitride fluorescent material having high emission luminance can be provided. The method includes heat-treating a raw material mixture containing silicon nitride, silicon, an aluminium compound, a calcium compound, and a europium compound.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 26, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Kazuya Nishimata, Hiroyuki Watanabe, Shoji Hosokawa
  • Patent number: 10658314
    Abstract: Disclosed herein is a wafer laminate suitable for production of thin wafers and a method for producing the wafer laminate. The wafer laminate can be formed easily by bonding between the support and the wafer and it can be easily separated from each other. It promotes the productivity of thin wafers. The wafer laminate includes a support, an adhesive layer formed on the support, and a wafer which is laminated on the adhesive layer in such a way that that surface of the wafer which has the circuit surface faces toward the adhesive layer, wherein the adhesive layer is a cured product of an adhesive composition composed of resin A and resin B, the resin A having the light blocking effect and the resin B having the siloxane skeleton.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 19, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Hideto Kato
  • Patent number: 10651210
    Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jee Hoon Kim, Shin Hyuk Yang, Yong Hoon Won, Kwang Soo Lee
  • Patent number: 10644044
    Abstract: Methods are provided for fabricating photodetector arrays using passive matrix addressing technology. The photodetector arrays use a pair of switching diode and photo diode to overcome crosstalk issues within the passive matrix. The switching diode and the photo diode of each pixel may be connected using a cathode-to-cathode connection, or an anode-to-anode connection. The photodetector arrays are fabricated by assembling on a first substrate, an array of photodetector pixels comprising a switching diode and a photo diode, providing conductive lines for each row of the array and conductive lines for each column of the array, and attaching a second substrate to the first substrate. The photodetector array may also be fabricated by assembling on a first substrate an array of switching diodes, and assembling on a second substrate an array of photo diodes, and bonding the first and second substrates together.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: National Research Council of Canada
    Inventors: Zhiyi Zhang, Ye Tao, Heping Ding, Salima Alem, Shoude Chang
  • Patent number: 10644057
    Abstract: An image sensor includes a photodiode disposed in a first semiconductor material to absorb photons incident on the image sensor and generate image charge. A floating diffusion is disposed in the first semiconductor material and positioned to receive the image charge from the photodiode, and a transfer transistor is coupled between the photodiode and the floating diffusion to transfer the image charge out of the photodiode into floating diffusion in response to a transfer signal. A source follower transistor with a gate terminal is coupled to the floating diffusion to output an amplified signal of the image charge in the floating diffusion. The gate terminal includes a second semiconductor material in contact with the floating diffusion, and a gate oxide is partially disposed between the second semiconductor material and the first semiconductor material. The second semiconductor material extends beyond the lateral bounds of the floating diffusion.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 5, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Xin Wang, Dajiang Yang, Siguang Ma, Keiji Mabuchi, Bill Phan, Duli Mao, Dyson Tai
  • Patent number: 10637211
    Abstract: A light-emitting semiconductor chip (100) is provided, having a first semiconductor layer (1), which is at least part of an active layer provided for generating light and which has a lateral variation of a material composition along at least one direction of extent. Additionally provided is a method for producing a semiconductor chip (100).
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: April 28, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Christoph Eichler, Andre Somers, Bernhard Stojetz, Andreas Loeffler, Alfred Lell
  • Patent number: 10626305
    Abstract: A barrier adhesive for the encapsulation of an (opto)electronic arrangement comprising an adhesive base composed of at least one reactive resin having at least one activatable group, at least one polymer, especially an elastomer, optionally at least one tackifying resin, where the adhesive base has a water vapour permeation rate after the activation of the reactive resin of less than 100 g/m2d, preferably of less than 50 g/m2d, especially less than 15 g/m2d, a transparent molecularly dispersed getter material and optionally a solvent, wherein the getter material is at least one silane having at least one alkoxy group and at least one activatable group.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: April 21, 2020
    Assignee: TESA SE
    Inventors: Klaus Keite-Telgenbüscher, Christian Schuh
  • Patent number: 10622215
    Abstract: A cutting apparatus includes a line sensor unit that applies a laser beam in a band shape elongated in a radial direction of a wafer to a region inclusive of a peripheral portion of the wafer held on a chuck table, and detects reflected light, and an information calculation section that calculates the position of the wafer and the height of the front surface of the wafer from the reflected light of the laser beam detected by the line sensor unit in a state in which the chuck table is rotated before the wafer is cut to form a stepped portion, and that calculates the width and the height of the stepped portion from the reflected light of the laser beam detected by the line sensor unit after the wafer is cut to form the stepped portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 14, 2020
    Assignee: DISCO CORPORATION
    Inventors: Atsushi Komatsu, Kokichi Minato
  • Patent number: 10622162
    Abstract: The present invention relates to a process for producing a layer of a crystalline material, which process comprises disposing on a substrate: a first precursor compound comprising a first cation and a sacrificial anion, which first cation is a metal or metalloid cation and which sacrificial anion comprises two or more atoms; and a second precursor compound comprising a second anion and a second cation, which second cation can together with the sacrificial anion form a first volatile compound. The invention also relates to a layer of a crystalline material obtainable by a process according to the invention. The invention also provides a process for producing a semiconductor device comprising a process for producing a layer of a crystalline material according to the invention. The invention also provides a composition comprising: (a) a solvent; (b) NH4X; (c) AX; and (d) BY2 or MY4; wherein X, A, M and Y are as defined herein.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 14, 2020
    Assignee: OXFORD UNIVERSITY INNOVATION LIMITED
    Inventors: Henry James Snaith, Wei Zhang, Michael Saliba