Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: Systems and methods for forming semiconductor layers, including oxide-based layers, are disclosed in which a material deposition system has a rotation mechanism that rotates a substrate around a center axis of the substrate. The system includes a heater configured to heat the substrate and a positioning mechanism that allows dynamic adjusting of an orthogonal distance, a lateral distance, and a tilt angle of an exit aperture of a material source relative to the substrate. In some embodiments, the dynamic adjusting is based on a desired layer uniformity for a desired layer growth rate. In some embodiments, the orthogonal distance, the lateral distance, or the tilt angle depends on a predetermined material ejection spatial distribution of the material source.

Abstract: Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate, an electrical component, and an EMI shield. The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device. The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Abstract: A display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer include a pad opening which exposes a portion of the data conductive layer in the pad area. The third data capping layer has a higher etch rate than the first and second data capping layers for a same etchant.

Abstract: The present invention relates to a method for forming an amorphous silicon thin film, a method for manufacturing a semiconductor device including the same, and a semiconductor device manufactured thereby. The present invention discloses a method for forming an amorphous silicon thin film, wherein the method includes a first step (S10) of providing a first gas containing silicon and a second gas containing nitrogen on a substrate (100) to form a first amorphous silicon layer (310b), and a second step (S20) of providing a first gas containing silicon on the substrate (100) having the first amorphous silicon layer (310b) formed thereon to form a second amorphous silicon layer (300a).

Abstract: A method of manufacturing a light-emitting device includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming, on or above the first surface of the substrate, a semiconductor structure comprising a light-emitting layer; forming a crack inside the substrate, the crack reaching the first surface of the substrate; disposing a wavelength conversion layer on the second surface of the substrate; forming a first recess in the wavelength conversion layer by removing a first portion of the wavelength conversion layer, the first portion overlapping with the crack when viewed in a direction from the wavelength conversion layer toward the semiconductor structure, and leaving a second portion of the wavelength conversion layer between the first recess and the semiconductor structure; and cleaving the second portion along the crack.

Abstract: A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.

Abstract: Exemplary deposition methods may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. The method may include striking a plasma in the processing region between a faceplate and a pedestal of the semiconductor processing chamber. The pedestal may support a substrate including a patterned photoresist. The method may include maintaining a temperature of the substrate less than or about 200° C. The method may also include depositing a silicon-containing film along the patterned photoresist.

Abstract: A semiconductor device with favorable electric characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer includes a region in contact with the first insulating layer, the first conductive layer is connected to the oxide semiconductor layer, and the second conductive layer is connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween.

Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

Abstract: One or more semiconductor structures and/or methods for forming support structures for semiconductor structures are provided. A first porosification layer is formed over a semiconductor substrate. A first epitaxial layer is formed over the first porosification layer. A second porosification layer is formed from a first portion of the first epitaxial layer and a support structure is formed from a second portion of the first epitaxial layer.

Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.

Abstract: Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

Abstract: The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.

Abstract: A display device includes a substrate including a display unit including a plurality of pixels and a protrusion protruding from an edge of the display unit, the plurality of pixels including a first pixel on an outermost region of the display unit and a second pixel adjacent to the first pixel; a driver on the protrusion; and a fan-out line to electrically connect the first pixel and the driver, wherein at least a portion of the fan-out line is on the display unit between the first pixel and the second pixel in a plan view.

Abstract: An oxide thin film transistor includes an oxide active layer, a first loose layer and a first oxygen release layer. The first loose layer is at least disposed on a first surface of the oxide active layer perpendicular to a thickness direction of the oxide active layer, and is in contact with the oxide active layer. A material of the first loose layer includes a first inorganic oxide insulating material. The first oxygen release layer is disposed on a surface of the first loose layer facing away from the oxide active layer, and is in contact with the first loose layer. A material of the first oxygen release layer is a first oxygen-containing insulating material.