Patents Examined by Bo B Jang
  • Patent number: 10522428
    Abstract: A method for critical dimension control in which a substrate is received having an underlying layer and a patterned layer formed on the underlying layer, the patterned layer including radiation-sensitive material and a pattern of varying elevation with a first critical dimension. The method further includes applying an overcoat layer over the patterned layer, the overcoat layer containing a photo agent selected from a photosensitizer generator compound, a photosensitizer compound, a photoacid generator compound, a photoactive agent, an acid-containing compound, or a combination of two or more thereof. The overcoat layer is then exposed to electromagnetic radiation, wherein the dose of electromagnetic radiation incident upon different exposed regions of the substrate is varied, and then the overcoat layer and patterned layer are heated. The method further includes developing the overcoat layer and the patterned layer to alter the first critical dimension of the patterned layer to a second critical dimension.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 31, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. deVilliers, Michael A. Carcasi
  • Patent number: 10522402
    Abstract: Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate, the dielectric lines raised above the metal lines. A hardmask layer is formed on the metal lines of the lower metallization layer, between and co-planar with the dielectric lines of the lower metallization layer. A grating structure is formed above and orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. A mask is formed above the grating structure. Select regions of the hardmask layer are removed to expose select regions of the metal lines of the lower metallization layer. Metal vias are formed on the select regions of the metal lines of the lower metallization layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventor: Leonard P. Guler
  • Patent number: 10522388
    Abstract: An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 31, 2019
    Assignee: Tower Semiconductor Ltd.
    Inventors: Einat Ophir Arad, Sharon Levin, Allon Parag, Eran Lipp, Yosef Avrahamov
  • Patent number: 10522744
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a metal oxide (Mox) layer and a tunnel barrier layer to produce interfacial perpendicular magnetic anisotropy (PMA). The Mox layer has a non-stoichiometric oxidation state to minimize parasitic resistance, and comprises a dopant to fill vacant lattice sites thereby blocking oxygen diffusion through the Mox layer to preserve interfacial PMA and high thermal stability at process temperatures up to 400° C. Various methods of forming the doped Mox layer include deposition of the M layer in a reactive environment of O2 and dopant species in gas form, exposing a metal oxide layer to dopant species in gas form, and ion implanting the dopant. In another embodiment, where the dopant is N, a metal nitride layer is formed on a metal oxide layer, and then an anneal step drives nitrogen into vacant sites in the metal oxide lattice.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu
  • Patent number: 10510739
    Abstract: A method of providing a layout design of an SRAM cell includes: providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area; forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout; forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout; forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and forming a second pull-down transistor on the second oxide diffusion area and second first polysilicon layout.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Tetsu Ohtou, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen
  • Patent number: 10503321
    Abstract: The present disclosure provides an optical sensing unit, a touch panel, a method for manufacturing the optical sensing unit, a method for manufacturing the touch panel, and a display device. The optical sensing unit includes a Photo thin film transistor (TFT), a storage capacitor for storing a leakage current generated by the Photo TFT, and a Readout TFT for reading out an electric signal stored in the storage capacitor. The method for manufacturing the optical sensing unit includes a step of forming a gate electrode of the Readout TFT capable of shielding an active layer of the Readout TFT and preventing the active layer from being exposed to an ambient light beam.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: December 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunwei Wu, Chungchun Lee, Yanfeng Wang, Xiaoguang Xu
  • Patent number: 10497859
    Abstract: A two-dimensional magnetic field sensor comprises a support, a single magnetic field concentrator which consists of at least three parts which are separated from each other by gaps, and at least two magnetic sensor elements. The magnetic sensor elements are arranged in the region of the edge of the magnetic field concentrator. No magnetic sensor element is present in the gaps.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: December 3, 2019
    Assignee: Melexis Technologies SA
    Inventor: Robert Racz
  • Patent number: 10497743
    Abstract: An optoelectronic device including a light emitting component and a field-effect transistor, the optoelectronic device including a first semiconductor layer made of a III-V or II-VI compound doped a first conductivity type; an active layer of the light-emitting component; and a second semiconductor layer made of the III-V or III-VI compound doped a second conductivity type opposite the first type, the active layer being sandwiched between the first and second semiconductor layers, wherein the channel of the field-effect transistor is located in the first semiconductor layer, the first semiconductor layer being uninterrupted between the field-effect transistor and the lightemitting component.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: December 3, 2019
    Assignee: Commissariat à I'Énergie Atomique et aux Énergies Alternatives
    Inventors: Ivan-Christophe Robin, Hubert Bono, Thierry Bouchet, Matthew Charles, René Escoffier, Erwan Morvan
  • Patent number: 10497720
    Abstract: A display device includes a driving gate electrode, a scan line separate from the driving gate electrode, a data line, a driving voltage line, and a semiconductor area including a first channel region overlapping the driving gate electrode and a shielding area overlapping the first data line. The display device also has a control line which includes a main line portion and a detour portion. The main line portion and the detour portion extend in different directions, and the semiconductor area includes a second channel region overlapping the first portion of the detour portion.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Won Choi, Chang Soo Pyon
  • Patent number: 10490596
    Abstract: A method for fabricating an image sensor is provided. In the method, at first, a semiconductor substrate having a top portion and a bottom portion is provided. Then, a light-sensitive element is formed in the bottom portion of the semiconductor substrate. Thereafter, the top portion of the semiconductor substrate is etched to form a post structure on the bottom portion of the semiconductor substrate. Thereafter, a gate dielectric layer and a conductive layer are sequentially formed to cover the bottom portion of the semiconductor substrate and the post structure. Then, the gate dielectric layer and the conductive layer are etched to form a vertical gate structure on the light-sensitive element.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 10453870
    Abstract: A flexible display substrate and a display device are disclosed. The flexible display substrate includes a plurality of signal lines located in a display area; a driver chip bound in a peripheral area; a plurality of lead wires configured to connect the driver chip with the signal lines, where both ends of each signal line correspond respectively to at least one lead wire. Both ends of a signal line can be arranged as such to correspond respectively to at least one lead wire, that is, the same signal line can correspond to at least two lead wires extended from an output end of the driver chip.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 22, 2019
    Assignees: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Tingliang Liu, Zhonglin Cao, Pengcheng Zang, Yuanjie Xu, Yang Wang
  • Patent number: 10453935
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10446593
    Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 15, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Francois Guyader
  • Patent number: 10446574
    Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. Dielectric constant (k) of the first material is less than 5.0. Sum of bandgap (BG) and electron affinity (chi) of the second material is no greater than 6.7 eV. The k of the second material is at least 5.0. Sum of BG and chi of the third material is less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 10438960
    Abstract: Each memory cell is of the type with charge trapping in a dielectric interface and includes a state transistor selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate. The columns of memory cells include pairs of twin memory cells. The two selection transistors of a pair of twin memory cells have a common selection gate and the two state transistors of a pair of twin memory cells have a common control gate. The device also includes, for each pair of twin memory cells, a dielectric region situated between the control gate and the substrate and overlapping the common selection gate so as to form on either side of the selection gate the two charge-trapping dielectric interfaces respectively dedicated to the two twin memory cells.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 8, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 10438941
    Abstract: A semiconductor apparatus including a substrate, an electrostatic discharge protection device, a resistor device, and a first metal layer is provided. The substrate defines a pad area and includes a first area and a second area. The first area has a recess, the second area is disposed in the recess, and the pad area is partially overlapped with the first area and the second area. The electrostatic discharge protection device is disposed in the first area of the substrate. The resistor device is disposed in the second area of the substrate. The first metal layer is disposed above and electrically connected to the electrostatic discharge protection device and the resistor device.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 8, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Yi-Yun Tsai, Chih-Hung Chen, Chin-Fu Chen
  • Patent number: 10438804
    Abstract: Methods and systems for using the downstream active residuals of a reducing-chemistry atmospheric plasma to provide multiple advantages to pre-plating surface preparation with a simple apparatus. As the downstream active species of the atmospheric plasma impinge the substrate surface, three important surface preparation processes can be performed simultaneously: 1. Organic residue is removed from the surface of the plating base. 2. Oxidation is removed from the surface of the plating base. 3. All surfaces on the substrate are highly activated by the downstream active residuals thus creating a highly wettable surface for subsequent plating operations.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 8, 2019
    Assignee: Ontos Equipment Systems
    Inventor: Eric Frank Schulte
  • Patent number: 10429453
    Abstract: The magnetic sensor includes a semiconductor substrate having Hall elements on a front surface of the semiconductor substrate, an adhesive layer formed on a back surface of the semiconductor substrate, and a magnetic flux converging plate formed on the adhesive layer. The magnetic flux converging plate is formed on the back surface of the semiconductor substrate through formation of the magnetic flux converging plate by electroplating on a base conductive layer formed on a plating substrate prepared separately from the semiconductor substrate, application of an adhesive for forming the adhesive layer onto a surface of the magnetic flux converging plate so that the magnetic flux converging plate adheres to the back surface of the semiconductor substrate, and peeling off of the plating substrate afterward from the base conductive layer formed on the magnetic flux converging plate.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 1, 2019
    Assignee: ABLIC INC.
    Inventors: Takaaki Hioka, Mika Ebihara, Hiroshi Takahashi, Matsuo Kishi, Miei Takahama
  • Patent number: 10424524
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 24, 2019
    Assignees: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD., BEIJING ESWIN TECHNOLOGY CO., LTD.
    Inventors: Minghao Shen, Xiaotian Zhou
  • Patent number: 10424618
    Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Stephen W. Russell, Tony M. Lindenberg