Abstract: The present invention provides a CMP abrasive slurry for polishing insulation film, that allow efficiently and high-speed polishing of insulation films such as SiO2 film and SiOC film in the CMP method of flattening an interlayer insulation film, a BPSG film, an insulation film for shallow trench isolation, or a wiring-insulating film layer, a polishing method by using the abrasive slurry, and a semiconductor electronic part polished by the polishing method. A CMP abrasive slurry for polishing insulation film containing cerium oxide particles, a dispersant, a water-soluble polymer having amino groups on the side chains and water, a polishing method by using the CMP abrasive slurry, and a semiconductor electronic part polished by the polishing method.

Abstract: A remote plasma source comprises a first plate-like electrode (7s) and a second plate-like electrode (7b) which are arranged in parallelism and mutually electrically DC isolated. The two electrodes (7s, 7b) are operationally connected to an Rf generator (11). The first electrode (7s) has a surface which is freely exposed to a substrate holder (3) and has a pattern of through-openings (19) distributed along its surface extent.

Abstract: Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

Abstract: A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer.

Abstract: A method for forming a micro-pattern in a semiconductor device includes forming a hard mask layer and a sacrificial layer over an etch target layer, forming a plurality of openings having a hole shape in the sacrificial layer, forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings, etching the sacrificial layer outside of the sidewalls of the openings using the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns, wherein the first area is smaller than the second area, and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns.

Abstract: A method and system for fabricating magnetic recording transducer are described. The magnetic recording transducer has a main pole including a plurality of sides, an intermediate layer adjacent to the sides of the main pole, and a field region distal from the main pole. The method and system include providing at least one trench in the intermediate layer. The trench(es) are between the main pole and the field region. The method and system also include providing a stop layer. A portion of the stop layer resides in at least part of the trench(es) and on at least part of the field region. The method and system also include removing a portion of the intermediate layer using a wet etch. The stop layer is resistant to removal by the wet etch. The method and system also include depositing a full wrap-around shield layer on the main pole.

Abstract: A method of patterning an insulation layer is described. The method includes preparing a film stack on a substrate, wherein the film stack comprises a cap layer, a SiCOH-containing layer overlying the cap layer, and a hard mask overlying the SiCOH-containing layer. The method further includes transferring a pattern through the film stack by performing a series of etch processes in a plasma etching system, wherein the series of etch processes utilize a temperature controlled substrate holder in the plasma etching system according to a substrate temperature control scheme that achieves etch selectivity between the SiCOH-containing layer and the underlying cap layer.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract: A method for performing a selective etching process is described. The method includes preparing a substrate having a silicon layer (Si) and a silicon-germanium (SiGex) layer, and selectively etching the silicon layer relative to the silicon-germanium layer using a dry plasma etching process.

Abstract: Radial distribution of etch rate is controlled by controlling the respective duty cycles of pulsed VHF source power applied to the ceiling and pulsed HF or MF bias power on the workpiece. Net average electrical charging of the workpiece is controlled by providing an electronegative process gas and controlling the voltage of a positive DC pulse on the workpiece applied during pulse off times of the pulsed VHF source power.

Abstract: A polishing slurry used in chemical mechanical polishing of a barrier layer and an interlayer dielectric film in a semiconductor integrated circuit includes an abrasive, an oxidizer, an anticorrosive, an acid, a surfactant and an inclusion compound. The polishing slurry has a pH of less than 5. The resulting polishing slurry contains a solid abrasive used in barrier CMP for polishing a barrier layer made of a metallic barrier material, has excellent storage stability, achieves a good polishing rate in various films to be polished such as the barrier layer, and is capable of independently controlling the polishing rate with respect to the various films to be polished while further suppressing agglomeration of the abrasive particles.

Abstract: A near-field light generating element has an outer surface including first and second inclined surfaces and an edge part that connects the first and second inclined surfaces to each other. In a method of manufacturing the near-field light generating element, a polishing stopper layer is initially formed on a metal layer, and the polishing stopper layer and the metal layer are etched so that the metal layer is provided with the first inclined surface. Next, a coating layer is formed to cover the metal layer and the polishing stopper layer. The coating layer is made of a non-metallic inorganic material that has an etching rate lower than that of the metal layer in a second etching step to be performed later. Next, the coating layer is polished until the polishing stopper layer is exposed. Next, the second etching step is performed to etch the polishing stopper layer and the metal layer using the coating layer as the etching mask.

Abstract: Diamond electrodes with improved adhesion of the diamond layer to the electrode are produced by sandblasting a surface of the electrode body, and then non-oxidatively etching the roughened (sandblasted) surface so as to remove at least 5 ?m of material from under the roughened surface. By removing at least 5 ?m of material, the sand particulates in the surface of the electrode body are eliminated, and damage in the form of cracks in the electrode body which result from sandblasting is reduced or eliminated, and further, a surface metal oxide coating is not created. All of these contribute to preparing a surface where spalling of the diamond layer is less likely to occur. Concentrated phosphoric acid is an exemplary non-oxidative etchant used in the process.

Abstract: The present invention provides such a formation method that an antireflection structure having excellent antireflection functions can be formed in a large area and at small cost. Further, the present invention also provides an antireflection structure formed by that method. In the formation method, a base layer and particles placed thereon are subjected to an etching process. The particles on the base layer serve as an etching mask in the process, and hence they are more durable against etching than the base layer. The etching rate ratio of the base layer to the particles is more than 1 but not more than 5. The etching process is stopped before the particles disappear. It is also possible to produce an antireflection structure by nanoimprinting method employing a stamper. The stamper is formed by use of a master plate produced according to the above formation method.

Abstract: A polishing liquid composition includes composite oxide particles containing cerium and zirconium, a dispersing agent, and an aqueous medium. A powder X-ray diffraction spectrum of the composite oxide particles obtained by CuK?1 ray (?=0.154050 nm) irradiation includes a peak (first peak) having a peak top in a diffraction angle 2? (? is a Bragg angle) range of 28.61 to 29.67°, a peak (second peak) having a peak top in a diffraction angle 2? range of 33.14 to 34.53°, a peak (third peak) having a peak top in a diffraction angle 2? range of 47.57 to 49.63°, and a peak (fourth peak) having a peak top in a diffraction angle 2? range of 56.45 to 58.91°. A half-width of the first peak is 0.8° or less.

Abstract: A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.

Abstract: A method of manufacturing a semiconductor device which includes a gate electrode formed in the shape substantially vertical to a semiconductor substrate is disclosed. A gate electrode is formed by anisotropically etching a gate electrode film having a metal-containing film formed on the semiconductor substrate via a gate insulating film to expose a portion of the gate insulating film. A modified film is formed on a side wall of the metal-containing film by modifying the side wall of the metal-containing film. The exposed portion of the gate insulating film is removed and a portion of the gate insulating film sandwiched between the semiconductor substrate and the metal-containing film is recessed so as to recede from the modified side wall of the metal-containing film by isotropically etching. A side portion of the metal-containing film protruding from the receded gate insulating film is removed by isotropically etching.

Abstract: The present invention relates to a method of fabricating a nanostructure, comprising the following steps: prestructuring a substrate (1) adapted to receive the nanostructure to form a nanorelief (2) on the substrate, the nanorelief having flanks (4) extending from a bottom (1a) of the substrate and a top face (3) extending from said flanks, and then depositing on the substrate pre-structured in this way a single layer or multilayer coating intended to form the nanostructure; and further comprising: adding to the prestructured substrate or to the coating a separation layer adapted to enable separation of the coating and the substrate by external action of mechanical, thermomechanical or vibratory type; and exerting this external action on the substrate and/or the coating to recover selectively a top portion of the coating by separating it from the top face of the nanorelief so that this top portion constitutes some or all of the nanostructure.

Abstract: According to a first aspect of the invention, a method for manufacturing a concave-convex pattern includes the steps of heating a sheet-like member, compressively bonding the sheet-like member, removing the sheet-like member after the compressively bonding, and transferring a pattern shape of a reverse concave-convex pattern layer to a surface of the substrate. The sheet-like member has a concave-convex pattern block on at least one of surfaces thereof, and is given flowability thereto by heating. The reverse concave-convex pattern layer is formed on the one of the surfaces, and continues over two or more concaves of the concave-convex pattern block so that the reverse concave-convex pattern layer meshes at least partially with the concave-convex pattern block. At least the reverse concave-convex pattern layer is left on the substrate. Here, the one of the surfaces has the concave-convex pattern block.

Abstract: Chemical polishing solutions and methods are disclosed for the chemical polishing of GaAs wafers. An exemplary chemical polishing solution consistent with the innovations herein may comprise dichloroisocyanurate, sulfonate, acid pyrophosphate, bicarbonate and carbonate. An exemplary chemical polishing method may comprise polishing a wafer in a chemical polishing apparatus in the presence of such a chemical polishing solution. Chemical polishing solutions and methods herein make it possible, for example, to improve wafer quality, decrease costs, and/or reduce environmental pollution.