Abstract: The optimization of circuit parameters of variational quantum algorithms is a challenge for the practical deployment of near-term quantum computing algorithms. Embodiments relate to a hybrid quantum-classical optimization methods. In a first stage, analytical tomography fittings are performed for a local cluster of circuit parameters via sampling of the observable objective function at quadrature points in the circuit parameters. Optimization may be used to determine the optimal circuit parameters within the cluster, with the other circuit parameters frozen. In a second stage, different clusters of circuit parameters are then optimized in “Jacobi sweeps,” leading to a monotonically convergent fixed-point procedure. In a third stage, the iterative history of the fixed-point Jacobi procedure may be used to accelerate the convergence by applying Anderson acceleration/Pulay's direct inversion of the iterative subspace (DIIS).

Abstract: The present invention relates to a wireless charging device including a communication signal compensator, a communication signal compensator comprises a power detector configured to detect a magnitude of a communication signal received through each of the plurality of antennas, and a control unit configured to acquire a communication signal having the greatest signal magnitude as the detection result, select an antenna corresponding to the communication signal having the greatest signal magnitude among the plurality of antennas, and transmit, to the coupling antenna, a switch control signal for controlling the switch to be connected to the selected antenna.

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: Swap insertion in mapping logical qubits on a quantum circuit is performed by obtaining an operation sequence including a plurality of operations to be executed on a quantum circuit. The quantum circuit including a plurality of physical qubits and a plurality of couplings. Finding a blocking set of operations including leading unresolved operation in the operation sequence. Calculating a first coupling score for each coupling of the plurality of couplings based on total reduction of shortest path lengths of a plurality of unresolved operations of the plurality of operations Selecting a coupling based on the first coupling score of each coupling. Updating the blocking set by removing any leading unresolved operations from the blocking set that can be performed after swapping a pair of logical qubits stored in a pair of physical qubits connected by the selected coupling.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: A method includes assigning a first color group to a first routing track of the layout. The method further includes assigning a second color group to a second routing track of the layout. The method includes assigning the first color group to a third routing track of the layout, wherein the second routing track is between the first routing track and the third routing track. The method further includes assigning a first color from the first color group to a first conductive element along the first routing track. The method further includes assigning a second color from the first color group to a second conductive element along the first routing track. The method further includes assigning a third color from the second color group to a third conductive element on the second routing track, wherein the third color is different from each of the first color and the second color.

Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.

Abstract: A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.

Abstract: Disclosed herein are several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift , tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing assist features onto or adjusting positions and/or shapes existing assist features in the portion. Adjusting the illumination source and/or the assist features may be by an optimization algorithm.

Abstract: A method of designing a chip having an integrated circuit is provided. The method includes obtaining delta cell delays and delta net delays according to a process, voltage, and temperature (PVT) corner change with respect to a plurality of cells and a plurality of nets forming the integrated circuit; analyzing sensitivity with respect to a delay according to the PVT corner change of a plurality of paths in the integrated circuit, by using the delta cell delays and the delta net delays; determining N-number of sensitivity-critical paths among the plurality of paths based on a result of the analysis, wherein N is an integer greater than or equal to 0; and performing an engineering change order (ECO) based on a result of the determination.

Abstract: The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.

Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

Abstract: A wireless automatic charging system for electric vehicles is disclosed, wherein the electric vehicle comprises a charging board, a Bluetooth device, a battery, as well as a battery management module electrically connected to the aforementioned charging board, Bluetooth device and battery and capable of detecting and recording the charging efficiency data concerning the charging board, and wherein the wireless automatic charging system for electric vehicles comprises a base seat, an air inflation and deflation device, a discharging board and a control console, wherein the battery management module in the electric vehicle can transfer the charging-related information of the electric vehicle to the control console via the Bluetooth module such, and adjust the distance between the charging board and the discharging board and/or charging power of the discharging board in accordance with the received charging efficiency data and the charging efficiency adjustment data.

Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Abstract: The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.

Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.

Abstract: Techniques and systems for inserting repeaters in an integrated circuit (IC) design are described. Some embodiments can place a snapping region in the IC design, wherein the snapping region includes a predetermined arrangement of feasible grid regions and blocked grid regions, and wherein repeaters are allowed to be placed in feasible grid regions but not in blocked grid regions. Next, the embodiments can iteratively perform a set of operations, comprising: selecting a net from a set of nets; determining an initial location for inserting a repeater in the net; identifying an unoccupied feasible grid region in the first snapping region that is closest to the initial location; and inserting a repeater in the net in the unoccupied feasible grid region.