Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Abstract: A light-emitting semiconductor chip, a light-emitting component and a method for producing a light-emitting component are disclosed. In an embodiment a light-emitting semiconductor chip includes a light-transmissive substrate having a top surface, a bottom surface opposite the top surface, a first side and a second side surface arranged opposite the first side surface, a semiconductor body arranged on the top surface of the substrate and a contacting including a first current distribution structure and a second current distribution structure, wherein the first current distribution structure and the second current distribution structure are freely accessible from a side of the semiconductor body facing away from the substrate, and wherein the semiconductor chip, on the side of the semiconductor body facing away from the substrate and on the bottom surface of the substrate, is free of any connection point configured to electrically contact the first and second current distribution structures.

Abstract: A display apparatus, comprising an element substrate including a display portion formed by arraying a plurality of organic light emitting elements on a base and a connecting portion provided on the base so as to be separated from the display portion, a driving substrate connected to the connecting portion so as to be configured to drive the display portion, and a heat-insulating portion provided between the display portion and the connecting portion in planar view in the base and configured to have lower heat conductivity than the base.

Abstract: Provided is a light-emitting diode (LED) display unit group and a display panel. The LED display unit group includes a circuit board, and a pixel unit array located on the circuit board. The pixel unit array includes a plurality of pixel units arranged in n rows and m columns, n and m are both positive integers and greater than or equal to 2. Each of the pixel units includes multiple LED light-emitting chips of at least two colors, each of the LED light-emitting chips includes an electrode A and an electrode B of opposite polarities. The LED light-emitting chip of each of the pixel units includes at least one dual-electrode chip, the dual-electrode chip has the electrode A and the electrode B located on a same side of the dual-electrode chip. All dual-electrode chips in the plurality of pixel units of a same color have connecting lines from the electrode A to the electrode B directed in a same direction.

Abstract: A device is disclosed. The device includes a tetragonal Heusler compound of the form Mn3-xCoxGe, wherein 0<x?1, wherein Co accounts for at least 0.4 atomic percent of the Heusler compound. The device also includes a substrate oriented in the direction (001) and of the form YMn1+d, wherein Y includes an element selected from the group consisting of Ir and Pt, and 0?d?4. The tetragonal Heusler compound and the substrate are in proximity with each other, thereby allowing spin-polarized current to pass from one through the other. In one aspect, the device also includes a multi-layered structure that is non-magnetic at room temperature. The structure includes alternating layers of Co and E. E includes at least one other element that includes Al. The composition of the structure is represented by Co1-yEy, with y being in the range from 0.45 to 0.55.

Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

Abstract: The present disclosure discloses a three-dimensional photodetector and a method of manufacturing the same. The three-dimensional photodetector according to an embodiment of the present disclosure includes a base part formed in the center region of the three-dimensional photodetector; a first bending part formed around the base part; at least one branch part connected to the base part through the first bending part; second bending parts formed on the at least one branch part; bonding parts connected to the at least one branch part through the second bending parts; at least one photoresistor formed on the surface of at least one of the base part and the branch parts; and a stretchable substrate to which the bonding parts are attached, wherein the bonding parts are attached to the stretchable substrate so that the base part has a gap in the thickness direction of the stretchable substrate; and the at least one photoresistor is responsible for tracking the traveling direction of light.

Abstract: An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90 and a connection body 50 having a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75. The head part 40 has a second projection protruding 42 toward the electronic element 95 and a first projection 41 protruding from the second projection 42 toward the electronic element 95.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. According to embodiments of the present disclosure, the manufacturing method of a display substrate comprises: fabricating a gate electrode, a gate electrode insulating layer, and a semiconductor active layer sequentially on a base substrate; fabricating a first etching stopping layer and a second etching stopping layer on the base substrate with the semiconductor active layer fabricated thereon, wherein the first etching stopping layer is disposed in a display area of the display substrate, the second etching stopping layer is disposed in a peripheral area of the display substrate, and the second etching stopping layer is a non-transparent layer; and fabricating source/drain electrodes by a patterning process, on the base substrate with the first and second etching stopping layers fabricated thereon, wherein the second etching stopping layer is used as an alignment marker in fabricating the source/drain electrodes.

Abstract: A display device includes: a substrate; a semiconductor layer of a transistor, on the substrate; a gate electrode of the transistor on the semiconductor layer; and a conductive layer element corresponding to the transistor. The conductive layer element is both electrically connected to a constant voltage source and contacts the substrate.

Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: An image sensor includes: a pixel substrate that includes a plurality of pixels each having a photoelectric conversion unit that generates an electric charge through photoelectric conversion executed on light having entered therein and an output unit that generates a signal based upon the electric charge and outputs the signal; and an arithmetic operation substrate that is laminated on the pixel substrate and includes an operation unit that generates a corrected signal by using a reset signal generated after the electric charge in the output unit is reset and a photoelectric conversion signal generated based upon an electric charge generated in the photoelectric conversion unit and executes an arithmetic operation by using corrected signals each generated in correspondence to one of the pixels.

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.

Abstract: The present invention provides an array substrate and a method of fabricating the same, wherein the array substrate includes a base substrate, a gate layer, a gate insulating layer, a source/drain layer, a first passivation layer, a color resist layer and a second passivation layer, wherein a passivation layer via hole is provided above the source/drain layer, and gas in the color resist layer releases from a surface of the color resist layer on a side of the passivation layer via hole. The invention realizes the purpose of completely discharging the gas in the color resist layer before a cell formation process.

Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.

Abstract: A semiconductor device and a method of manufacturing the same are provided such that a microelectromechanical systems (MEMS) element is protected at an early manufacturing stage. A method for protecting a MEMS element includes: providing at least one MEMS element, having a sensitive area, on a substrate; and depositing, prior to a package assembly process, a protective material over the sensitive area of the at least one MEMS element such that the sensitive area of at least one MEMS element is sealed from an external environment, where the protective material permits a sensor functionality of the at least one MEMS element.

Abstract: An elementary cell includes a non-volatile resistive random-access memory mounted in series with a volatile selector device, the memory including an upper electrode, a lower electrode and a layer made of a first active material, designated memory active layer. The selector device includes an upper electrode, a lower electrode and a layer made of a second active material, designated selector active layer. The cell includes a one-piece conductor element including a first branch having one face in contact with the lower surface of the memory active layer in order to form the lower electrode of the memory, a second branch having one face in contact with the upper surface of the selector active layer in order to form the lower electrode of the memory.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may include removing of an exposed portion of a CEM film to form an exposed sidewall region bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay. The method may further include at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.