Abstract: Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate and bonding the semiconductor substrate to a carrier. The semiconductor substrate includes an inert material layer and a semiconductor layer on the inert material layer. The semiconductor substrate is bonded to the carrier such that the inert material layer is between the carrier and the semiconductor substrate. By including an inert material layer between the carrier and the semiconductor substrate, a barrier against diffusion for any bonding agents used to bond the semiconductor substrate to the carrier is formed, thereby preserving the integrity of the semiconductor layer and allowing for the easy removal of the semiconductor substrate from the carrier.

Abstract: The present invention describes a method for producing CdTe thin-film solar cells, in which special parameters of different processing steps and a special sequence of processing steps result in improved characteristics of the produced CdTe solar cells.

Abstract: An electronic element mounting substrate includes a first substrate including a first main surface and a mounting portion in a rectangular shape for mounting an electronic element, positioned on the first main surface and one end portion of the mounting portion in a longitudinal direction being positioned at an outer edge portion of the first main surface and a second substrate positioned on a second main surface opposite to the first main surface, formed of a carbon material, and including a third main surface facing the second main surface and a fourth main surface opposite to the third main surface. A thermal conduction of the mounting portion in a direction perpendicular to in a longitudinal direction is greater than a thermal conduction of the mounting portion in the longitudinal direction, in the third main surface or the fourth main surface, in plan view.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a transformer formed in the insulating layer, and a wiring. The transformer includes a primary winding conductor, and a secondary winding conductor. The primary winding conductor is provided in a quadrangle spiral shape having a first center axis extending in a direction parallel to the surface of the semiconductor substrate inside the insulating layer, and configured by one conductor film selected from a group consisting of a vacuum deposition film, a chemical vapor deposition film and a sputtered film. The secondary winding conductor is provided in a quadrangle spiral shape having a second center axis inside the insulating layer while being spaced from the primary winding conductor in plan view of the semiconductor substrate, magnetically coupled with the primary winding conductor and configured by a conductor film.

Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.

Abstract: A display device may include a display panel including a substrate that includes a display area and a pad area adjacent to the display area, and a first pad and a second pad on the pad area of the substrate, and a chip-on-film package over the pad area of the substrate with the first pad and the second pad in between, the chip-on-film package including an insulation layer, a first wiring on an upper surface of the insulation layer and electrically connected to the first pad, and a second wiring on a lower surface of the insulation layer and electrically connected to the second pad. A first signal having alternating voltage levels may be applied to the first wiring, and a second signal having a constant voltage level may be applied to the second wiring.

Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

Abstract: The present disclosure proposes a cover plate for an organic electroluminescent display device and a method for manufacturing the same. The cover plate for the organic electroluminescent display device includes: an auxiliary electrode disposed on a substrate to be electrically connected to an electrode of the organic electroluminescent display device; and a light reflection suppression structure disposed on the auxiliary electrode and configured to suppress reflection of light from a surface of the auxiliary electrode. The present disclosure further proposes an organic electroluminescent display device and a display apparatus.

Abstract: A method for producing an illumination device may include providing a plurality of optoelectronic semi-conductor components that each have a semi-conductor layer sequence for generating radiation where the semiconductor components each have at least one contact surface on one side and are held by a common carrier. The method may further include electroplating each contact surface of the semi-conductor components using a solder material, applying the semi-conductor components having the solder material to a substrate, and melting and soldering the contact surfaces onto the surfaces.

Abstract: A method includes forming a semiconductor fin over a substrate; forming a plurality of isolation structures adjacent to the semiconductor fin; etching the semiconductor fin to form a recess between the isolation structures; forming a first epitaxy layer in the recess; forming a second epitaxy layer over the first epitaxy layer; forming a third epitaxy layer over the second epitaxy layer, in which the first epitaxy layer has a higher germanium (Ge) concentration than the second and third epitaxy layers; etching the third epitaxy layer; and forming a dielectric layer in contact with the third epitaxy layer after etching the third epitaxy layer.

Abstract: A semiconductor laminate includes a substrate formed of a group III-V compound semiconductor and a quantum well structure disposed on the substrate. The quantum well structure includes a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer. In the first element layer, the thickness of a region in which the content of Sb decreases in a direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, an insulative material may be formed on or over a sidewall portion of a conductive contact region. The insulative material may insulate the conductive contact region from resputtered CEM occurring during a physical etch of a CEM film.

Abstract: In a first step of a method of manufacturing a semiconductor device, a portion to be the first lead frame is formed by selectively punching a metal plate, furthermore, notch portions depressed in the reference direction are formed on both side surfaces of a portion, of the first lead frame where the first bent portion is formed, in line contact with the first conductive layer in the reference direction; in the second step of the method, a first bent portion is formed by bending the one end of the first lead frame so as to protrude downward along the reference direction; and in the third step of the method, the upper surface of the first conductive layer and the lower surface of the first bent portion of the first lead frame are joined at the end of the substrate, by the first conductive bonding material, furthermore, the upper surface of the first conductive layer and the notch portions of the first bent portion are joined, by embedding a part of the first conductive bonding material in the notch portions.

Abstract: The one end portion of the connector of the semiconductor device includes: a horizontal portion; a first inclined portion that is connected to the horizontal portion and is located closer to the tip end side of the one end than the horizontal portion, and the first inclined portion having a shape inclined downward from the horizontal portion; and a control bending portion that is connected to the first inclined portion and positioned at the tip of the one end portion, and the control bending portion bent downwardly along the bending axis direction. The lower surface of the control bending portion is in contact with an upper surface of the second terminal.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin on a substrate. A dummy gate structure is formed crossing the semiconductor fin. The dummy gate structure is replaced with a metal gate structure. An epitaxial structure is formed in the semiconductor fin after replacing the dummy gate structure with the metal gate structure.

Abstract: Magnetic structures including magnetic inductors and magnetic tunnel junction (MTJ)-containing structures that have tapered sidewalls are formed without using an ion beam etch (IBE). The magnetic structures are formed by providing a material stack of a dielectric capping layer and a sacrificial dielectric material layer above a lower interconnect level. First and second etching steps are performed to pattern the sacrificial dielectric material layer and the dielectric capping layer such that a patterned dielectric capping layer is provided with a tapered sidewall. After removing the sacrificial dielectric material layer, a magnetic material-containing stack is formed within the opening in the patterned dielectric capping layer and atop the patterned dielectric capping layer. A planarization process is then employed to pattern the magnetic-containing stack by removing the magnetic material-containing stack that is located atop the patterned dielectric capping layer.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.

Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.