Abstract: A feedback 1T DRAM device that has a partial insulating film structure is provided. A body region may be divided into two or more in a channel direction by pn junctions and/or partial insulating layers, and gates may be formed on each of the divided body regions. The present invention can be operated by filling and subtracting electrons in the energy well of the conduction band and holes in the energy well of the valence band, respectively. In addition, it is possible to maximize retention time and improve operation reliability by reducing carrier loss by energy barriers of pn junctions and/or partial insulating layers.

Abstract: An organic light-emitting diode (OLED) display panel and a manufacturing method thereof are provided. The OLED display panel includes an array substrate and a cathode structure. The cathode structure includes a metal film layer. The metal film layer includes a first metal film layer and a second metal film layer. The first metal film layer is positioned within the first active area and the second metal film layer is positioned within the second active area. Different regions of the metal film layer in the cathode structure are adjusted to different thicknesses, so that different regions have different light transmittances, which is beneficial to increase screen-to-body ratio.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating diodes. In one aspect, an electrical circuit includes: (1) a diode component having a particular energy band gap; (2) an electrical source electrically coupled to the diode component and configured to bias the diode component in a particular state; and (3) a heating component thermally coupled to a junction of the diode component and configured to selectively supply heat corresponding to the particular energy band gap.

Abstract: The present application discloses a thin-film transistor (TFT) array substrate and a display panel. The TFT array substrate includes an active layer and a source/drain electrode disposed on the active layer. The active layer includes an electrode coverage region, a channel region, and a first peripheral region disposed around the electrode coverage region and the channel region. The active layer located in the first peripheral region is distributed in multi-sections.

Abstract: In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

Abstract: The present invention generally relates to a method for preparing structurally unique nanomaterials and the products thereof. In particular, the present invention discloses a method for preparing an array of ultra-narrow nanowire or nanorod on a patterned monolayer supported by a 2D material substrate in a controlled environment, wherein said pattered monolayer comprises a polymerizable amphiphiles such as phospholipid with a terminal amine and wherein said controlled environment comprises a major nonpolar solvent, a trace amount of polar solvent, and a unsaturated aliphatic amine. Gold nanowires (AuNWs) so prepared have a highly controlled diameter of about 2 nm, a length up to about 1000 nm, and an AuNW ordering over an area >100 ?m2.

Abstract: A heterostructure includes a substrate exhibiting a piezoelectric effect, and a magnetostrictive film supported by the substrate. The magnetostrictive film includes an iron-gallium alloy. The iron-gallium alloy has a gallium composition greater than 20%.

Abstract: Provided are methods for obtaining n-type doped metal chalcogenide quantum dot solid-state films. In some embodiments, the methods include forming an metal chalcogenide quantum dot solid-state film, carrying out a n-doping process on the metal chalcogenide quantum dots of the metal chalcogenide quantum dot solid-state film so that they exhibit intraband absorption, wherein the process includes partially substituting chalcogen atoms by halogen atoms in the metal chalcogenide quantum dots and providing a substance on the plurality of metal chalcogenide quantum dots, to avoid oxygen p-doping of the metal chalcogenide quantum dots. Also provided are optoelectronic devices, which in some embodiments can include an n-type doped metal chalcogenide quantum dot solid-state film (A) obtained by a method as disclosed herein and first (E1) and second (E2) electrodes in physical contact with two respective distanced regions of the film (A).

Abstract: The present disclosure is related to a semiconductor device and a method of manufacturing the said semiconductor device. The semiconductor device comprising a stacked configuration of a plurality of semiconductor layers. At least one of the semiconductor layers is a III-V compound semiconductor layer, and at least one of the III-V compound semiconductor layers has formed thereonto a corresponding crystalline terminating oxide layer, wherein the at least one of the plurality of semiconductor layers interfaces via its crystalline terminating oxide layer to a neighbouring epitaxial semiconductor layer thereto. The semiconductor device is a quantum well device.

Abstract: A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.

Abstract: Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

Abstract: An embodiment of a semiconductor device includes a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction. A body region of a first conductivity type adjoins a sidewall of the trench gate structure and includes a first body sub-region adjoining the sidewall and a second body sub-region adjoining the sidewall. At least one profile of dopants of the first conductivity type along the vertical direction includes a first doping peak in the first body sub-region and a second doping peak in the second body sub-region. A doping concentration of the first doping peak is larger than a doping concentration of the second doping peak.

Abstract: An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm·cm2, preferably less than 5 mOhm·cm2.

Abstract: A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged.

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

Abstract: A display device comprises a substrate having a plurality of sub-pixels; a plurality of LEDs respectively disposed in the plurality of sub-pixels, wherein each of the LEDs comprises an emissive layer, a first semiconductor layer between the substrate and the emissive layer and a second semiconductor layer on the emissive layer; a plurality of driving units disposed under the substrate in each of the sub-pixels; and a plurality of connection units penetrating the substrate and electrically connecting at least one of the first semiconductor layer and the second semiconductor layer with the plurality of driving units.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: A method for transferring a superficial layer from a detachable structure comprises the following steps: a) supplying the detachable structure comprising: •a support substrate, •a detachable layer arranged on the support substrate along a main plane and comprising a plurality of walls that are separated from one another, each wall having at least one side that is perpendicular to the main plane; •a superficial layer arranged on the detachable layer along the main plane; b) applying a mechanical force configured to cause said walls to bend, along a direction that is secant to said side, until causing the mechanical rupture of the walls, in order to detach the superficial layer from the support substrate.

Abstract: Patterned ceramic wavelength-converting phosphor structures may be bonded to an LED to form a pcLED. The phosphor structures are patterned with features that provide enhanced oxygen permeability to an adhesive bond used to attach the phosphor structure to the LED. The enhanced oxygen permeability reduces transient degradation of the pcLED occurring in the region of the adhesive bond.

Abstract: An optoelectronic component may have a semiconductor chip designed to emit electromagnetic radiation. The semiconductor chip may have a radiation exit surface, and a protective layer arranged over the radiation exit surface. The protective layer may include at least one first layer comprising an aluminum oxide and at least one second layer comprising a silicon oxide a silicon oxide, and at least one third layer comprising a titanium oxide. A current spreading layer may include one or more transparent conductive oxides arranged between the radiation exit surface and the protective layer.