Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract: Optical films, and organic light-emitting display devices employing the same, include a high refractive index pattern layer including a lens pattern region and a non-pattern region alternately formed, wherein the lens pattern region includes a plurality of grooves each having a depth larger than a width thereof, and the non-pattern region has no pattern; and a low refractive index pattern layer formed of a material having a refractive index smaller than a refractive index of the high refractive index pattern layer, wherein the low refractive index pattern includes a plurality of filling portions filling the plurality of grooves.

Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

Abstract: A method of manufacturing a solid state image sensor is provided. The method includes forming electrically conductive layer and an interlayer insulation film above a first region and a second region, performing an annealing process after forming the conductive layer and the interlayer insulation film, and forming a protective film above the interlayer insulation film and the electrically conductive layer. The electrically conductive layer includes a light shielding layer arranged above the second region. The interlayer insulation film includes a first portion located above the first region and a second portion located above the second region and below the light shielding layer. Before performing the annealing process, an average hydrogen concentration of the second portion is higher than an average hydrogen concentration of the first portion.

Abstract: A display panel is provided. The display panel includes has an active area and a border area surrounding the active area. The display panel includes a plurality of pixels, a plurality of multiplexer portion, a gate driver portion and a source routing portion. The pixels are located in the active area. The multiplexer portion is located in the border area. The gate driver portion is located in the border area. The source routing portion is located in the border area. In part of the border area, at least part of the multiplexer portion, at least part of the gate driver portion and at least part of the source routing portion are located and sequentially arranged from an internal edge of the border area to an external edge of the border area.

Abstract: The present invention is to provide an hermetic-sealing package member including a substrate and at least one frame-like sealing material for defining a sealing region formed on the substrate, in which the sealing material is formed of a sintered body obtained by sintering at least one metal powder selected from gold, silver, palladium, or platinum having a purity of 99.9 wt % or greater and an average particle size of 0.005 ?m to 1.0 ?m, and with respect to an arbitrary cross-section toward an outside from the sealing region, a length of an upper end of the sealing material is shorter than a length of a lower end. Examples of a cross-sectional shape of the sealing material may include one formed to have a base portion having a certain height and at least one mountain portion protruding from the base portion or one formed to have a mountain portion having substantially a triangular shape in which the length of the lower end of the sealing material is a bottom.

Abstract: A magnetoresistive random-access memory (MRAM) cell with a dual sidewall spacer structure is provided. The MRAM cell includes an anti-ferromagnetic layer, a pin layer, a free layer, a first sidewall spacer layer, and a second sidewall spacer layer. The pin layer is arranged over the anti-ferromagnetic layer and has a fixed magnetic polarity. The free layer is arranged over the pin layer and has a variable magnetic polarity. The first sidewall spacer layer extends from over the pin layer along sidewalls of the free layer. The second sidewall spacer layer extends from over the anti-ferromagnetic layer along sidewalls of the pin layer and the first sidewall spacer layer. A method for manufacturing the MRAM cell is also provided.

Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.

Abstract: The present disclosure relates to an organic image sensor and an associated method. By inserting an inorganic protective layer between an electrode and an organic photo active region of the image sensor, the organic photo active region is protected from moisture, oxygen or following process damage. The inorganic protective layers also help to suppress the leakage in the dark. In some embodiments, the organic image sensor comprises a first electrode, an organic photoelectrical conversion structure disposed over the first electrode and a second electrode disposed over the organic photoelectrical conversion structure. The organic image sensor further comprises a first protective structure covering a top surface and a sidewall of the organic photoelectrical conversion structure.

Abstract: When an uneven pattern is formed on a light extraction surface composed of a semiconductor crystal by wet-etching using an alkaline solution, a plurality of convex portions cannot be formed in a desired arrangement. A method of manufacturing a semiconductor light emitting device includes a light extraction surface composed of a semiconductor crystal, wherein when the uneven pattern is formed by a plurality of convex portions on the light extraction surface, first, a plurality of impressions are formed on the light extraction surface of a semiconductor layer composed of a semiconductor crystal using a processing substrate, and next, by applying wet-etching to the light extraction surface using an alkaline solution, to thereby form convex portions with a portion where each impression is formed as a top portion, and a plurality of facets of the semiconductor crystal as a side face thereof.

Abstract: According to one embodiment, a semiconductor package includes: a first metal body on which a part of a waveguide structure is formed; a second metal body including a mounting area for a semiconductor device and disposed on the first metal body; a line substrate on which a signal transmission line configured to communicate a waveguide with the semiconductor device mounted on the mounting area is formed; and a lid body disposed at a position facing the first metal body, interposing the second metal body and the line substrate. The lid body is made of resin, on which a structure corresponding to another waveguide structure on an extension of the waveguide structure in the first metal body is formed. The structure includes a metal-coated inner wall surface.

Abstract: Disclosed are GaN based light emitting devices and methods of manufacturing the same using post-mechanical treatment. The GaN based light emitting device includes first and second electrodes, and a flexible substrate which are sequentially stacked, an n-type GaN layer, an activation layer, and a p-type GaN layer interposed between the first and second electrodes and forming a core-shell structure, and a buried layer interposed between the flexible substrate and the first electrode, wherein the first electrode and the core-shell structure are buried in the buried layer.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract: In the technical field of display, a display device for solving the technical problem of H-block caused by the resistance of the wire on array is provided. The display device comprises a substrate, a gate driver circuit, and at least two chip on films for transmitting the gate driving signal. The display device further comprises at least two wirings, each chip on film being connected to the gate driver circuit through one of the wirings. The wirings each comprise a wire on array, and all or some of the wirings each further comprise a resistor in series connection with the wire on array thereof. The present disclosure can be applied to display devices, such as liquid crystal television, liquid crystal display, cell phone, and tablet PC, and the like.

Abstract: A microphone device includes a carrier board, a micro electro-mechanical system unit, an integrated circuit and an upper cover. The micro electro-mechanical system unit includes a substrate, a cap and a capacitive microphone. The cap is installed on the substrate, and is composed of electrically conductive material. The capacitive microphone is positioned between the cap and the carrier board, wherein the capacitive microphone and the cap form a resonant cavity. The integrated circuit is installed on the carrier board, and arranged to control the capacitive microphone. The upper cover is connected to the carrier board, wherein the micro-electro mechanical system unit and the integrated circuit are both positioned inside a space formed by the carrier board and the upper cover.

Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.

Abstract: Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and a first passivation layer; a second die including a second pad and a second passivation layer; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer includes: a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and a third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer.