Patents Examined by Brendan Mee
  • Patent number: 6153081
    Abstract: A method of recovering antimony and bismuth from copper electrolyte comprises the steps of immersing a pure copper material in the copper electrolyte, so that the iron ions are reduced from Fe.sup.3+ ions to Fe.sup.2+ ions, using a mixture of dilute sulfuric acid and sodium chloride adjusting the acidity or acidic concentration, to selectively elute the bismuth and antimony wherein if the final concentration of bismuth is adjusted to be 0.02 g/l or less in the bismuth election, it is possible to keep the maximum concentration of bismuth in the antimony eluate in the elution of antimony after selective bismuth elution to 0.01 g/l or less.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: November 28, 2000
    Inventors: Atsushi Fukui, Naoyuki Tsuchida, Kouji Ando
  • Patent number: 5967795
    Abstract: A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards its outermost edge.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: October 19, 1999
    Assignee: Asea Brown Boveri AB
    Inventors: Mietek Bakowsky, Bo Bijlenga, Ulf Gustafsson, Christopher Harris, Susan Savage
  • Patent number: 5858819
    Abstract: In order to fabricate a high performance thin film semiconductor device using a low temperature process in which it is possible to use low price glass substrates, a thin film semiconductor device has been fabricated by forming a silicon film at less than C., and, after crystallization, keeping the maximum processing temperature at or below C.In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: January 12, 1999
    Assignee: Seiko Epson Corporation
    Inventor: Mitsutoshi Miyasaka
  • Patent number: 5855756
    Abstract: An electrorefining cell permits increased electrolyte flow rates while maintaining the slime layer at the bottom of the cell and on the anode faces substantially intact. The cell includes an inlet manifold located near the bottom of the cell and having a plurality of discharge orifices for the electrolyte solution. An inlet baffle shrouds the discharge orifices to regulate and direct the flow of electrolyte solution within the cell. The inlet baffle and the cell wall form an elongated slot that resides beneath the surface of the electrolyte solution. An analogous configuration is employed for electrolyte discharge to enable relatively high electrolyte flow into and out of the cell. The specific shape, size, and location of the inlet baffle and an outlet baffle may be selected to optimize the electrolyte flow characteristics of the cell.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: January 5, 1999
    Assignee: BHP Copper Inc.
    Inventor: Gerald C. Anzalone, III
  • Patent number: 5843833
    Abstract: A metal element density is lowered in a crystalline silicon film obtained by four hour treatment at about C. by using a catalyst metal which accelerates crystallization. At the same time, a crystalline silicon film can be obtained which has a high crystallinity. For this purpose, extremely oxide film 13 is formed on an amorphous silicon film formed on this glass substrate in the beginning. An aqueous solution of acetate added with 10 to 200 ppm (need adjustment) of catalyst element like nickel or the like is dripped. This state is held for a predetermined time. Then the spin drying is performed by using a spinner. The film is crystallized by four hour treatment at C. Then a localized nickel component is removed by the fluoric acid treatment. Further, the crystalline silicon film is obtained by laser light irradiation. Then a crystalline silicon film is obtained having a low density of metal element and a small defect density by four hour heat treatment at C.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: December 1, 1998
    Assignee: Semiconductor Energy Laboratroy Co., Ltd.
    Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
  • Patent number: 5837120
    Abstract: A continuous strip is electrochemically processed in an electrolytic processing bath using either a thin flexible or resilient dielectric wiping blade or an open web, plastic mesh to wipe bubbles of gas from the surface, sever dendritic material, if such is present, and to remove a surface layer of partially depleted electrolytic solution, replacing with fresh solution and to stabilize strip portions extending between support rolls. The resilient dielectric wiper blade is preferably used with perforated anodes which allow fresh electrolytic solution to flow into the space between the anodes and the strip surface after being expelled by passage of the strip past the wiping blade. The wiping blades may also be angularly oriented with respect to the strip to increase the wiping effectiveness.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: November 17, 1998
    Assignee: Electroplating Technologies, Inc.
    Inventors: James L. Forand, Harold M. Keeney, Erik S. Vananglen
  • Patent number: 5837119
    Abstract: Methods for forming pastes of dendrites particles coated with an electrically conductive coating are described. A surface is placed in contact with an electrolytic or electroless plating solution. Dendrites are formed on the surface. The dendrites are exposed to another plating solution to plate a coating on the surface of the dendrites. The coated dendrites are removed from the surface to form a powder of coated dendrites. The powder is added to a polymer material to form a paste which is heated to fuse the dendrite surfaces to form a network of interconnected dendrites and further heated to cure the polymer. When the paste is disposed between adjacent electrically conductive surfaces, the coated dendrites fuse to the electrically conductive surface to form electrical interconnections.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: November 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: Sung Kwon Kang, Sampath Purushothaman, George Frederick Walker
  • Patent number: 5837156
    Abstract: The two sides of a multiple cavity mold having electroformed mold cavities for molding intraocular lenses with integral haptics are made by a preferred electroforming procedure involving the use of either a single primary master having a single cavity corresponding to the portion of the lens at either side of its median plane transverse to its optic axis if the lens to be molded is symetrical about both this transverse median plane and its longitudinal median plane containing the optic axis, or a pair of primary masters having single cavities, respectively, corresponding to the portions of each lens at opposite sides of its transverse median plane if the lens is unsymmetrical about either plane.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: November 17, 1998
    Inventor: J. Stuart Cumming
  • Patent number: 5837118
    Abstract: A method of producing a hollow electroformed product of precious metal includes the steps of forming a hollow soluble metal electroformed layer soluble in an inorganic acid on the outer surface of a master model formed of a low melting point material or a chemically soluble material soluble in a chemical, melting or dissolving and removing the master model from inside the soluble metal electroformed layer, coating the outer surface of the remaining soluble metal electroformed layer with a masking layer, forming a precious metal electroformed layer on the inner surface of the soluble metal electroformed layer, stripping the masking layer, and dissolving the soluble metal electroformed layer with inorganic acid.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: November 17, 1998
    Assignee: M. Yasui & Co., Ltd.
    Inventors: Shozui Yasui, Tetsuya Kotoda
  • Patent number: 5827411
    Abstract: Methods, and various apparatus therefor, are disclosed for the electrolytic treatment of an acidic solution. Generally the method comprises: (a) providing an electrolytic cell, the cell comprising: (i) an anode chamber and an anode therein; (ii) a cathode chamber and a cathode therein; and (iii) a diaphragm. Usually the diaphragm is of a non-isotropic fibrous mat comprising 5-70 weight percent organic halocarbon polymer fiber in adherent combination with about 30-95 weight percent of finely divided inorganic particulate impacted into said fiber during fiber formation, the diaphragm having a weight per unit of surface area of about 3-12 kilograms per square meter. The method can continue by (b) introducing the acidic solution into the cell; (c) impressing a current on the anode and the cathode causing the migration of ions through the diaphragm; and (d) recovering a product of the electrolytic treatment from the anode chamber, or the cathode chamber, or from both chambers.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: October 27, 1998
    Assignee: Eltech Systems Corporation
    Inventors: Jeries I. Bishara, Roland J. Horvath, Anthony R. Sacco, Jean M. Hinden
  • Patent number: 5824203
    Abstract: A method and means for changing the characteristics of a substance, particularly a viscous substance, involves passing the substance into a path, passing a solvent for that substance into the path, and subjecting the substance and the solvent to a pulsating electric field in the frequency range of 0.1 Hz to 100 Hz.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: October 20, 1998
    Assignee: SGI International
    Inventor: John L. Remo
  • Patent number: 5817560
    Abstract: A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: October 6, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Fred N. Hause
  • Patent number: 5811328
    Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: September 22, 1998
    Assignee: Semiconductor Energy Laboratory Co, Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 5807469
    Abstract: A cathode contact device is provided for providing particle deposition from an anode source onto a target surface of a working piece. The working piece has a first electrically conductive continuous contact surrounding the target surface. The cathode contact device includes a second electrically conductive continuous contact adapted for frictionally contacting the first contact along a continuous path located on the first contact. The second contact further has an inner periphery defining an aperture for passing therethrough the particles onto the target surface. Additionally, the cathode contact device includes a circuit for electrically coupling the second contact to an electrical current supply.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: September 15, 1998
    Assignee: Intel Corporation
    Inventors: Douglas E. Crafts, Steven M. Swain, Kenji Takahashi, Hirofumi Ishida
  • Patent number: 5804473
    Abstract: A method for fabricating a thin film semiconductor device includes the steps of introducing, into an amorphous film of a semiconductor material, at least one metallic element that forms an intermetallic compound with the semiconductor material and at least one nonmetallic element selected from group VIa elements, group VIIa elements or nitrogen, and crystallizing the amorphous film, after introducing the metallic element and the nonmetallic element, by a thermal annealing process, to convert the amorphous film to a crystalline film.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: September 8, 1998
    Assignee: Fujitsu Limited
    Inventor: Yutaka Takizawa
  • Patent number: 5804497
    Abstract: A selectively doped MOS transistor channel includes a deep impurity distribution and shallow impurity distribution. The deep impurity distribution is formed within high energy implant with an impurity of conductivity type opposite to the conductivity type of the source/drain regions of the transistor. In the n-channel regions, the deep impurity distribution preferably includes boron ions. The deep impurity distribution acts as a channel stop such that adjacent source/drain regions of the like type transistors are not inadvertently coupled during circuit operation. The shallow impurity distribution acts as a threshold implant by precisely controlling the doping of the transistor channel in the vicinity of the silicon oxide interface. The peak concentration of the shallow impurity distribution is located at a depth below the silicon surface which is greater than a depth typically associated with a threshold adjust implant.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: September 8, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr., Fred N. Hause
  • Patent number: 5795815
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: August 18, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5795816
    Abstract: Method of fabricating a thin-film transistor. This transistor has a semiconductor such as a silicon semiconductor. This semiconductor is irradiated with pulsed laser light having a pulse width which is set greater than 1 .mu.s to maintain molten state of the silicon surface for a long time. As a result, a silicon film having high crystallinity can be obtained. This scheme can be used for crystallization of an amorphous silicon film and for activation effected after implantation of impurity ions.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: August 18, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Teramoto, Akira Takenouchi, Hisashi Ohtani
  • Patent number: 5779870
    Abstract: Drum or smooth side-treated metal foil can be used either as an intermediate product for use in the manufacture of laminate or as a part of the finished laminate to be used in the manufacture of multi-layer printed circuit board (PCB) packages. By treating the drum or smooth side of metal foil with a bond strength enhancer rather than treating the matte side or rough side, or both sides, several time-consuming and costly steps can be bypassed in the manufacture of multi-layer printed circuit boards (PCB) while the integrity of the metal foil, -laminate and multi-layer PCB are not compromised and are actually enhanced by way of improved impedance control and adhesion characteristics after relamination. This novel foil can be initially bonded to substrate on either side before circuit formation and can be used either as an internal foil layer or as a foil cap. The invention includes methods of manufacture of the metal foil, laminate and multi-layer printed circuit board.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: July 14, 1998
    Assignee: Polyclad Laminates, Inc.
    Inventor: D. Eric Seip
  • Patent number: 5776818
    Abstract: A method of fabricating a silicon structure including forming an insulating layer having an opening on single crystal semiconductor substrate; forming a polycrystalline semiconductor layer on the insulating layer and within the opening in the insulating lating layer; forming an anti-reflective film at spaced apart positions on the polycrystalline semiconductor layer spaced from the opening in the insulating layer by a substantially uniform distance; melting the polycrystalline semiconductor layer by laser irradiation and recrystallizing the polycrystalline semi-conductor layer into a single crystal layer including a quasi-grain boundary; and selectively implanting dopant impurities into the portion of the single crystal layer including the quasi-grain boundary.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: July 7, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Yamaguchi