Abstract: This invention concerns a method for epitaxial growth by the use of a so-called heterogeneous reaction and includes disposing a source material in a first area of a horizontal chamber, disposing a growth substrate in a second area thereof, heating the first area thereby keeping the source material at a first temperature, heating the second area thereby keeping the growth substrate at a second temperature, lower than the first temperature, introducing a reaction gas into the chamber thereby causing the reaction gas to react with the source material and depositing the resultant reaction product on the growth substrate and consequently obtaining formation of a film by epitaxial growth.

Abstract: After an interconnection layer such as Al alloy is formed on an insulating film covering the surface of a substrate, a connection hole is formed through a laminate of the insulating film and the interconnection layer at the area corresponding to the region to be connected. An adhesion layer such as TiN is formed on the interconnection layer, covering the inner surface of the connection hole, and thereafter a conductive layer such as W is formed on the adhesion layer by blanket CVD, burying the inside of the connection hole. The conductive layer is etched back to leave part of the conductive layer in the connection hole as a plug. Through interconnection patterning, an interconnection having a desired pattern is formed which is constituted by the remaining portions of the interconnection layer, the adhesion layer, and the plug. The adhesion layer functions as an antireflection layer during the interconnection patterning.

Abstract: A method for carrying out crystallization by annealing with good throughput on a large-area semiconductor thin film to constitute an active layer of thin film transistors integrally formed in a thin film semiconductor device. To manufacture a thin film semiconductor device, an amorphous semiconductor thin film is first formed on the surface of an insulating substrate 1 extending in the longitudinal direction and the cross direction, which are mutually orthogonal. An annealing step is then carried out wherein energy is applied from outside to transform the semiconductor thin film 2 from amorphous to polycrystalline form. Thin film transistors are then formed using this semiconductor thin film 2 as an active layer.

Abstract: Underplating between a metallic plating base and a photoresist deposited reon can be reduced or eliminated by a method of fabricating a microstructure which includes the steps of:(a) depositing a plating base on the adhesion layer;(b) depositing on the plating base a sacrificial layer of a material that reduces or eliminates underplating on the plating base compared to underplating in absence of the sacrificial layer;(c) depositing a photoresist on the sacrificial layer;(d) exposing, developing and removing the exposed photoresist from the substrate to uncover a portion of the sacrificial layer;(e) removing the sacrificial layer portion from the substrate to uncover a portion of the plating base; and(f) depositing a metallic material on the uncovered plating base under the influence of electrical current.

Abstract: A crystallization process comprising the steps of depositing a polycrystalline silicon layer on a semiconductor substrate, implanting silicon ions into first and second areas of the polycrystalline silicon layer in different amounts such that crystals having a predetermined plane direction remain in the second area and such that the first area becomes amorphous, and performing a thermal treatment to recrystallize the amorphous second area using the crystals having the predetermined plane direction remaining in the first area as a nucleus.

Abstract: A method of fabricating a novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories is disclosed herein. Since the degree of ion implantation in the substrate determines the thichness of the silicon dioxide. The proper thickness of the silicon dioxide can be determined by considering the particular dopant to be used and degree of ion implantation, a 50-100 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E14-1E15 atoms/cm.sup.2, 100 KeV, ion implantation. A 150-350 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E11-1E13 atoms/cm.sup.2, 100 KeV, ion implantation.

Abstract: A method for producing a thin-film transistor (TFT) in which the gate electrode is offset from the source and drain without detriment to the characteristics of the device or to manufacturing yield, and a structure for such a TFT, are disclosed. A gate electrode is formed using a material capable of anodic oxidation, and a mask is formed on the gate electrode. Using a comparatively low voltage, a comparatively thick, porous anodic oxide film is formed on the sides of the gate electrode. The mask is then removed and using a comparatively high voltage a dense anodic oxide film is formed at least on the top of the gate electrode. Using the gate electrode having this anodic oxide on its top and sides as a mask, an impurity is introduced into the semiconductor film and an offset structure is obtained.

Abstract: There is provided manganese dioxide to be suitably used for alkaline manganese batteries and manganese batteries to make them excellent both in the initial performance and the storability. There is also provided a method of manufacturing such manganese dioxide. The electrolytic manganese dioxide has a BET specific surface area of less than 30 m.sup.2 /g (preferably less than 27 m.sup.2 /g) and a suspensiveness of less than 50 mg/liter. A method of manufacturing electrolytic manganese dioxide may be a suspension method, wherein manganese oxide is suspended at a rate of 0.01 to 0.2 g/liter in an electrolytic bath containing sulfuric acid at a concentration of 0.4 to 0.55 mol/liter and electrolyzed to produce electrolytic manganese dioxide with an anodic current density of 0.4 to 3.0 A/dm.sup.2 and an electrolytic temperature of 93.degree. to 103.degree. C., the relationship between the anodic current density and the electrolytic temperature being expressed by 103.gtoreq.y.gtoreq.1.67x+92.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a junction of an upper level transistor to a junction of a lower level transistor so as to effect direct coupling between series or parallel-coupled transistor pairs. Direct coupling in this fashion affords lower parasitic resistance and thereby achieves the benefit of a higher performance, faster switching circuit.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described.Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.

Abstract: A semiconductor device on a semiconductor wafer, wherein improvements are realized to agglomeration control, resistivity, and thermal stability of a titanium disilicide layer on a polysilicon layer. Agglomeration control is achieved through the use of two carefully selected low dose barrier diffusion matrix implants into the polysilicon layer, one of which is situated at an interface between the layer of polysilicon and the resultant layer of titanium disilicide film after heat treatment, and the other of which is near the surface of the resultant layer of titanium disilicide film after heat treatment.

Abstract: A method of fabricating a IC electrical plug, which removes an overhang to prevent formation of voids inside the plug. A transistor with a gate and source/drain terminals is formed on a silicon substrate. A dielectric layer is formed above the silicon substrate. A portion of the dielectric layer is removed by etching to form a contact window, exposing the source region, the drain region, or another conductive material region. A first diffusion barrier layer is formed at the bottom and on the sidewalls of the contact window, and on the top surface of the dielectric layer, overhanging the contact window. A photoresist layer is coated over the substrate filling up the contact window and covering the surface of first diffusion barrier layer.

Abstract: A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls.

Abstract: Improved thin film transistors to reduce defects in the devices incorporating the transistors, including active matrix displays. A first improvement is accomplished by forming a dual insulator layer over the bottom metal layer, which can be the gate line and also the row line in an active matrix display. The first insulator layer is formed by anodizing the metal layer and the second insulator layer is deposited onto the first layer. The dual insulator structure layer can be reanodized to eliminate the effect of pinholes. A second improvement includes providing an interdigitated transistor structure to increase the channel width, minimize internal shorting and minimize the drain capacitance. The interdigitated structure includes at least one source or drain finger formed between at least two drain or source fingers, respectively. A shorted source finger can be disconnected to maintain an operative transistor.

Abstract: A method for producing at least two transistors in one semiconductor body includes placing a first well doping region for receiving a first transistor and a second well doping region serving as a charge carrier sink region for a second transistor into a semiconductor body by masked doping with ensuing heat treatment. A mask for forming the second well doping region includes regions being permeable to a dopant and regions being impermeable to the dopant.

Abstract: A method for producing a multiplicity of microelectronic circuits on SOI uses a standardized process to produce n-CMOS or p-CMOS transistors, NPN-transistors or PNP-transistors, for instance. All that is required to do so is to adapt the implantations that are performed.

Abstract: A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes.

Abstract: A semiconductor device having a silicon-on-insulator structure, and a method for fabricating the semiconductor device, wherein a thick silicon oxide film is formed on each side wall of an active silicon substrate, thereby obtaining an increased threshold voltage at the edge of the active silicon substrate. The semiconductor device includes a first silicon substrate, a first silicon oxide film formed over the first silicon substrate, a second silicon substrate on the first silicon oxide film, second silicon oxide films, respectively disposed on opposite side walls of the second silicon substrate, a gate oxide film formed on the second silicon substrate, a gate electrode formed over the gate oxide film, and source/drain impurity diffusion regions, respectively formed in portions of the second silicon substrate disposed at both sides of the gate electrode.

Abstract: A MOSFET has shallow trenches of a thick oxide for isolating the MOSFET device from a surrounding substrate. The MOSFET has a gate wiring layer that includes co-aligned metallurgy of a predetermined work function at regions where the gate wiring layer passes over the oxide of the isolation trenches. The co-aligned metallurgy of predetermined work function is operative to increase the parasitic threshold voltage associated with the MOSFET's parasitic leakage currents.