Abstract: This invention is a process for fabricating a CMOS dynamic random access memory (DRAM) wherein a high-energy, oblique P-type implant is employed for punchthrough protection and field isolation enhancement or alternatively for punchthrough protection and as the sole field isolation implant. The process proceeds by forming P-type and N-type regions in a silicon substrate, performing an optional field isolation implant and forming field isolation regions using LOCOS or a modified LOCOS sequence, forming a gate dielectric layer, forming wordlines, depositing an offsetting dielectric layer, performing a low-dosage N-type implant in N-channel source/drain regions, forming spacers on the sidewalls of the gate electrodes, constructing cell capacitors superjacent the storage-node regions, performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers, and performing a high-dosage N-type implant in bitline contact regions.

Abstract: In a method for fabricating a CMOS device with NMOS and PMOS transistors, patterned nitride films are employed in the source/drain ion implantation procedure to reduce the required number of photolithography steps.

Abstract: Method for producing a silicon technology transistor on a nonconductor. This method consists in particular of forming a thin film of silicon (6) on a nonconductor (4) and then a mask (8, 10) including one opening (13) at the location provided for the channel (26) of the transistor; of locally oxidizing (14) the unmasked silicon to form an oxidation film; of eliminating the mask; of forming source (18) and drain (20) regions in the silicon by ion implantation with the oxidation film being used to mask this implantation; of eliminating the oxidation film; and of forming a thin gate nonconductor between the source and the drain and then forming the gate.

Abstract: A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

Abstract: Using a gate electrode formed on a semiconductor film as a mask, impurity ions are implanted into the semiconductor film. Thereafter, a photoresist film is formed on the substrate including the gate electrode. The photoresist film on the gate electrode is then exposed to light from a back side of the gate electrode. By this self-alignment method, a resist pattern narrower than the gate electrode is formed. Then, the gate electrode is narrowed through the etching thereof using the photoresist pattern as a mask, whereby an offset gate structure of a thin-film transistor is obtained.

Abstract: Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate.By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.

Abstract: The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.

Abstract: A CMOS device is provided with a deep collector guard ring. The guard ring is formed by thermally deep diffusing impurities from a poly layer into the surface of a well beneath the poly layer. The guard ring can thus be easily manufactured using CMOS compatible fabrication processes to a depth which is greater than the source and drain regions of the CMOS device.

Abstract: A polycrystalline silicon film pattern 3 having a thickness of below 120 nm is formed on a silicon oxide film 2 provided on the principal surface of a silicon substrate 1. The polycrystalline silicon film pattern 3 is covered with a boron silicate glass film 4. By heat treatment, boron is diffused from the boron silicate glass film 4 to the polycrystalline silicon film pattern 3 to form a polycrystalline silicon resistance element 5 containing boron at a density of above 1.times.10.sup.19 atoms/cm.sup.3. As a result, the temperature coefficient of the resistance element 5 comprising the polycrystalline film can be reduced.

Abstract: A channel stop is self-aligned with a trench sidewall of a trench-isolated semiconductor architecture, so that there is no alignment tolerance between the stop and the trench wall. An initial masking layer, through which the trench pattern is to be formed in a semiconductor island layer, is used as a doping mask for introducing a channel stop dopant into a surface portion of the semiconductor layer where the trench is to be formed. The lateral diffusion of the dopant beneath the oxide and adjacent to the trench aperture defines the eventual size of the channel stop. The semiconductor layer is then anisotropically etched to form a trench to a prescribed depth, usually intersecting the underlying semiconductor substrate. Because the etch goes through only a portion of the channel stop diffusion, leaving that portion which has laterally diffused beneath-the oxide mask, the channel stop is self-aligned with the sidewall of the trench.

Abstract: A bipolar transistor is formed on a substrate of a first (P) conductivity type by: forming a collector region (20) of the second conductivity type (N) in the substrate; forming an adjust region (27) of the first (P) conductivity type in the collector region (20); forming a base region (36) of the first (P) conductivity type in the collector region (20), the base region (36) containing the adjust region (27); and forming an emitter region (11) of the second (N) conductivity type in the adjust region (27). The base region (36) is deeper than and more heavily doped than the adjust region (27). The adjust region (27) alters the doping profile of the base-collector junction on the collector (20) side of the junction to increase the breakdown voltage of the transistor.

Abstract: One preferred method for making a semiconductor structure includes altering the direction, and optionally the position, of a polycrystalline grain boundary (38) in a base layer (17,21) of an epitaxial base bipolar transistor (10). Altering the grain boundary (38) may be accomplished by annealing the semiconductor structure after the layer, which later forms the lower portion of the base (17), has been deposited. Altering the grain boundary (38) has a significant effect in reducing base resistance (R.sub.bx1, R.sub.bx2). Reduced base resistance (R.sub.bx1, R.sub.bx2) dramatically improves device performance.

Abstract: In a gas pressure controlled processing chamber, a semiconductor package is enclosed by a heater and is heated extensively (or in a full-face way) up to a predetermined temperature equal to or higher than a fusing point of pre-solder bumps applied on bonding portions of a substrate and a cap of the semiconductor package in a state in which the bonding portions are separated from each other. After the predetermined temperature has been reached, the bonding portions are brought into abutment. In the abutting state of the bonding portions, a gas pressure in the processing chamber is controlled and the semiconductor package is cooled. The control of the gas pressure in the processing chamber is made by successively measuring a temperature of the semiconductor package and determining a control target value of the gas pressure in accordance with the measured temperature value. By this gas pressure control, a solder fillet profile is corrected.

Abstract: A thin-film transistor panel is constituted by forming, on an insulating substrate, a plurality of thin-film transistors, a plurality of gate lines for each connecting gate electrodes of the thin-film transistors, and a plurality of pixel electrodes formed of a transparent conductive film connected to the thin-film transistors, then forming a low-resistance metal film of an Al or Al alloy for a data line and a surface metal film of Cr with a high density, forming a photoresist film of a predetermined pattern on the surface metal film, and etching the data line metal film and surface metal film. Then, the surface metal film remaining on the data line metal film is eliminated.

Abstract: A self-aligned process for fabricating high performance bipolar transistors for integrated circuits includes the formation of a collector contact and intrinsic collector region within an opening at the face of a semiconductor substrate. In particular, layers of oxide and polysilicon are formed on the surface of a substrate. An opening is then formed in both layers followed by the implantation of a buried collector region into the substrate at the exposed substrate face through the opening. Polysilicon contacts to the buried layer are then formed on the sidewalls of the opening. These contacts join with the polysilicon layer to form a collector contact. An oxide is then grown on the collector contact. A monocrystalline intrinsic collector is then formed from the exposed substrate face adjacent said collector contact. In this manner, the buried collector, collector contact and intrinsic collector are all formed in a self-aligned manner.

Abstract: A method for planarization of the upper surface of a semiconductor wafer. A wafer with features formed thereon is loaded into the apparatus after having been coated with an interlevel dielectric. Thereafter, the wafer is subjected to suitably elevated temperature while a uniform elevated pressure is applied. Once the temperature and pressure conditions exceed the yield stress of the film, the film will flow and fill the microscopic as well as global depressions in the wafer surface. Thereafter, the temperature and pressure is reduced so that the film will become firm again thereby leaving a planar upper surface on the wafer.

Abstract: A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than about 600.degree. C. is sufficient to cause such oxidation, although some oxidation may occur at lower temperatures. The concentration of the fluorine-containing compound is also not critical, but is generally between about 100 to 1500 ppm by volume relative to the total mixture volume. Preferably, NF.sub.3 is the fluorine-containing compound, and a temperature greater than about 700.degree. C. at a concentration of between about 100 to 1000 ppm is used.

Abstract: A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

Abstract: A semiconductor package device is disclosed. In one embodiment, attached by its active face to a lead-on-chip leadframe having leadfingers is an integrated circuit. The integrated circuit has a polyimide coating on its backside. An encapsulating material surrounds the integrated circuit and the lead-on-chip leadframe so that the leadfingers are exposed. The polyimide coating on the backside of the integrated circuit helps to reduce package cracking arising from mounting the device to a printed circuit board by relflow solder.

Abstract: Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material over-hanging the opening along both its elongate sides and its ends. A contact metal is next evaporated both into the opening and onto the adjacent patterning material, with the overhang producing a continuous gap around the periphery of the gate contact between it and the metal on the adjacent patterning material. The adjacent metal is then lifted-off without disturbing the gate contact. The inward tapered profile in the elongate direction of the contact opening is achieved with multiple parallel e-beam scans, while a similar profile is achieved at the ends of the elongate scans by increasing the electron beam dose in the vicinity of the scan ends, preferably by scanning the beam at a substantial angle to the elongate direction near the ends of the opening.