Abstract: A liquid crystal image display device comprising an insulating substrate having plural scanning lines and signal lines and a switching device and a pixel electrode provided for each of pixels, a light-transmissive insulating substrate having a transparent conductive counter electrode and liquid crystal filled between both substrates, wherein said signal lines or scanning lines for supplying electric signals to said switching devices and conductive paths for connecting said switching devices with the pixel electrodes are coated with an thick organic film so as to be electrically isolated from said liquid crystal.

Abstract: A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/output transistors. All of the I/O devices on all sides of the array are oriented in the same common direction, which is the same direction as the orientation of the active transistor in the active region. This arrangement allows the use of the benefits of high angle ion implantation with fewer ion implant steps. Where some of the transistors are oriented at right angles to others, as in the prior art, four separate directions of high angle ion implantation are required to avoid degradation of electrical properties. With all transistors, including those of the gate array and those of the input/output devices, all oriented in the same direction, only two directions of high angle ion implantation are required.

Abstract: An AlGaAs chip which has an n-type layer and a p-type layer is immersed in an aqueous solution containing 0.2-0.6 wt. % of ammonia and 25-35 wt. % of hydrogen peroxide to form a primary protective layer, and after drying the AlGaAs chip, the AlGaAs chip is for a second time immersed in an aqueous solution containing 0.2-0.6 wt. % of ammonia and 25-35 wt. % of hydrogen peroxide to form a secondary protective layer.

Abstract: This is a semiconductor chip package configuration particularly suited for stacking. These described arrangement is especially adapted to be used with the so-called Lead-On-Chip type package. Each package is of minimum size, and provided with a thermal heat sink arranged with respect to the remainder of the package to balance the stresses induced in the package during fabrication. This is accomplished by placing a lead frame on the active face of the semiconductor chip, bonding the lead frame conductors to respective input/output pads on the active face of the chip, and molding an encapsulant completely around five of the six sides of the chip but leaving a substantial portion of the sixth side unencapsulated. A heat sink is affixed on the exposed, i.e. unencapsulated, portion of the sixth side of the chip.

Abstract: A method of manufacturing a semiconductor wafer, which includes performing a first metallization to deposit a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, depositing a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, etching via holes through the dielectric and spin-on glass layers to reach the tracks of the first interconnect layer, performing an in-situ desorption of physically and chemically bonded water vapour in a dry environment at a temperature of at least 400.degree. C. and not more than 550.degree. C. for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25.degree. C.

Abstract: A method for providing programmable devices in which an insulation layer, such as an oxide (20), TEOS, or the like, is formed during a BiCMOS integrated circuit fabrication process includes forming a first conductor fuse layer (22), for example of TiW or the like, on the insulation layer (20). The fuse layer (22) may then be patterned, and a second insulation layer (23) formed over it. Alternatively, the fuse layer (53) may be left unpatterned and one or more conductor layers (35,36) may be formed over the fuse layer (53). The conductor layer (35,36) is patterned, and the fuse layer (53) thereafter patterned using the conductor layer (35,36) as an etch mask. In either case, contact holes (26) are formed in the insulation layer (20) to regions (14,15) to which contact is desired under the insulation layer (20).

Abstract: A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjacent stripes are shifted or offset relative to each other. This causes the emitter pieces which are added to connect adjacent emitter stripes to be staggered with respect to each other. As a result, all sections of the emitters face a base contact and the resistance encountered along a current path between a base contact and an emitter is reduced. This results in a vertical bipolar transistor having a larger proportion of highly activated emitter, better high-frequency performance, and a reduction in thermal noise owing to transistor base resistance.

Abstract: A method for fabricating a contact plug capable of achieving a smooth tungsten growth by implanting silicon ions in the bottom surface of a via contact hole not only to remove a polymer formed on the bottom surface of the via contact hole, but also to provide a seed layer for the tungsten growth, and capable of preventing an adverse effect on the contact resistance resulting from a formation of AlF.sub.3 due to a direct contact between Al and WF.sub.6.

Abstract: The invention provides a continuous rapid thermal process for forming a substantially uniform oxynitride film on fingered three-dimensional silicon structures comprising cleaning of the silicon substrate and growth of silicon oxide in the presence of ozone, nitridation of the silicon oxide layer in the presence of NH.sub.3 and reoxidation of the oxynitride layer in the presence of oxygen.

Abstract: A silicon-on-insulator (SOI) material is formed from a bonded silicon wafer structure which includes, in order, a silicon handler substrate, an insulating oxide layer, a silicon device layer, a highly-doped silicon etch stop layer, and a top silicon substrate. The bonded silicon wafer structure is etched in a first anisotropic etching step to remove the top silicon substrate and expose the etch stop layer. Subsequently, a second anisotropic etching step is performed to remove a major portion but less than all of the etch stop layer, with the second anisotropic etching step continuing only until a substantially maximum degree of thickness uniformity is obtained in a remaining portion of the etch stop layer. The remaining portion of the etch stop layer is then removed, to yield a silicon-on-insulator material having a high degree of thickness uniformity.

Abstract: An integrated circuit microwave interconnect is formed upon a surface by disposing a dielectric layer over the surface and patterning the dielectric layer to form a dielectric region. The dielectric region is then surrounded by a surrounding metal layer. In one embodiment the surface may be a non-metal upon which a metal layer is disposed prior to disposing the dielectric layer. In this embodiment an additional metal layer is disposed adjoining the first metal surface on both sides of the dielectric region after patterning the layer to form the dielectric region. Thus, the two metal layers thereby form the surrounding metal layer around the dielectric region. The microwave interconnect may be formed upon the surface of the substrate, above the surface of the substrate in a floating configuration, or in a trench within the substrate.

Abstract: A new method for forming a planarized dielectric layer on a patterned conducting layer was accomplished. The method involves forming a insulating layer over a semiconductor substrate having semiconductor devices formed therein. A metal conducting layer is deposited and then patterned by anisotropically etching. The patterned conducting layer is used to make the electrical connections to the device contact. A barrier insulator is deposited on the patterned conducting layer to keep the conducting layer from coming into contact with the spin-on-glass and eroding. A planar dielectric layer is formed over the patterned conducting layer by coating a first spin-on-glass layer at a constant and low speed and then baking and then a second spin-on-glass layer is coated on the first spin-on-glass layer at a constant and high speed and then cured forming an improved planarized dielectric layer.

Abstract: A method for manufacturing bipolar semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters.

Abstract: A device for making temporary or permanent electrical connections to circuit pads of an integrated circuit is made with conventional semiconductor fabrication processes. The device has a supporting substrate from which project a plurality of insertion structures that are in mating alignment with corresponding circuit pads of the integrated circuit. Each insertion structure is metallized to make electrical contact with the corresponding circuit pad. The electrical contacts may be temporary or permanent depending upon the choice of metallization and the pressure applied to the contacting surfaces. The insertion structure devices have particular application for functional testing, electrical burn-in and packaging of an integrated circuit either as a full wafer or as an individual die.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: Disclosed is a method of manufacturing a semiconductor substrate by bonding two silicon crystalline wafers, and particularly, to a method of manufacturing a semiconductor substrate capable of reduced electrical resistance at the bonding interface. In the disclosed method, the silicon wafers to be bonded have at least one surface mirror-polished. Then they are washed, thus forming a natural oxide film on the surface. Then they are soaked in a concentrated HF solution for enough time to remove the oxide film formed on the surface. After that, the silicon wafers are soaked in ultra pure water to replace the fluorine atoms terminated on the surface thereof by OH groups, followed by drying. The silicon wafers thus treated are closely contacted with each other in such a manner that the mirror-polished surfaces are opposed to each other. The silicon wafers are thus bonded to each other by the hydrogen bonding forces due to the OH groups, and then heat treated for reinforcing the bonding.

Abstract: An improved insulated gate semiconductor device comprises a high-concentration p-type semiconductor region formed widely enough to protrude over n-type emitter regions without reaching an n-type epitaxial layer over a p-type base region only in first regions wherein the n-type emitter regions are wider than second regions as viewed from the top of the device. A gate threshold voltage V.sub.GE (th) has a relatively high level V.sub.GE (th-High) in the first regions, so that a low collector-emitter saturation voltage V.sub.CE (sat) and a low saturation current I.sub.CE (sat) are achieved. This provides for a high short-circuit tolerance as well as a high latch-up tolerance with low losses.

Abstract: Post-growth annealing of GaInSb/InAs superlattices at about 400.degree. to 650.degree. C. in an antimony flux followed by cooling results in enhanced optical properties as determined by photoluminescence and in reduced background doping levels as determined by Hall measurements. Accordingly, the annealing procedure represents an advantage over previous fabrication techniques for Ga.sub.1-x In.sub.x Sb/InAs superlattices.