Abstract: For removing contaminants (32) from a silicon substrate (31) having a principal surface (31a), a polycrystalline silicon film (34) is formed on an oxidation film (33) which is formed by oxidizing the principal surface. Selective oxidation is used. As a result, the contaminants are mainly concentrated around an interface between the oxidation and the polycrystalline silicon films. Thereafter, the oxidation and the polycrystalline silicon films are deleted from the silicon substrate. Therefore, the contaminants are eliminated from the silicon substrate together with the oxidation and the polycrystalline silicon films.

Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.

Abstract: An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure.

Abstract: A silicon-on-insulator (SOI) substrate is arranged such that a polycrystalline silicon film which functions as a gettering site for heavy metals is provided on a first single crystal silicon substrate, a silicon oxide island film is partially provided in a polycrystalline silicon film, and a second single crystal silicon substrate is provided on an entire upper surface of the polycrystalline silicon film. An element isolation trench extends from an upper surface of the second single crystal silicon substrate to an upper surface of the first single crystal silicon substrate, and a silicon oxide film is buried in the element isolation trench. The SOI substrate thus constituted has a high gettering effect for heavy metals.

Abstract: Trenches having different profiles are formed in a material, such as a semiconductor substrate, by forming a resist pattern having windows with at least two different widths. An etchant, such as Fluorine, is implanted into portions of the semiconductor using an ion implantation technique. A tilt angle and an azimuth angle of the ion beam are chosen such that the Fluorine ions cannot pass through narrower resist windows but can pass through wider resist windows to impinge on the underlying semiconductor substrate. The semiconductor substrate is then subjected to an anisotropic etching process. Accordingly, the substrate regions exposed between the narrow-width resist windows are etched to produce trenches having highly vertical profiles. The substrate regions exposed by the wide-width resist windows, including the regions having implanted etchant ions, are preferentially etched to produce trenches having tapered profiles.

Abstract: The present invention relates to a method of forming a double diffused metal-oxide-semiconductor (DMOS) transistor which enables the formation of short channels. This method uses silicon nitride sidewall spacers so that the sidewall spacers can be removed without etching the field oxide, therefore the length of the channel can be minimized to reduce the channel resistance.

Abstract: A method of forming a chlorinated silicon nitride barrier layer is disclosed. The method of the present invention includes depositing a silicon nitride layer over a semiconductor substrate. The silicon nitride layer is exposed to an ambient including chlorine at an elevated temperature for a predetermined time to form the chlorinated silicon nitride barrier layer that is resistant to attack by at least one reactive compound.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped polysilicon region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the polysilicon region. An oxide region is provided on a portion of the first region surface adjacent to the polysilicon region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a polysilicon region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the polysilicon region into the first region.

Abstract: A method of making high performance MOSFETs uses image reversal lithography to make punchthrough implants.

Abstract: A bipolar transistor and a PMOS device achieves improved performance through the use of borosilicate glass (BSG) as the sidewall spacer material. The sidewall spacer material also is used for injection of boron into adjacent substrate material for forming shallow p+ doped junctions. By using diffusion from the BSG to form and/or maintain (during subsequent processing) a bipolar base region, or a PMOS source and/or drain region, rather than ion implantation, a base region is formed which is both shallow and has a low sheet resistance.

Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

Abstract: Composite bond pad structure and geometry increases bond pad density and reduces lift-off problems. Bond pad density is increased by laying out certain non-square bond pads which are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith by a bond wire or lead frame lead and aligns to the approach angle of the conductive line to which it is connected. Alternating, interleaved, complementary wedge-shaped bond pads are discussed. Bond pad liftoff is reduced by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad and is filled with conductive material.

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract: A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film.This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH.sub.4 or Si.sub.2 H.sub.6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si.sub.2 H.sub.6 or SiH.sub.

Abstract: A IV-IV semiconductor device having a narrowed bandgap characteristic compared to silicon and method is provided. By incorporating carbon into silicon at a substitutional concentration of between 0.5% and 1.1%, a semiconductor device having a narrowed bandgap compared to silicon and good crystalline quality is achieved. The semiconductor device is suitable for semiconductor heterojunction devices that use narrowed bandgap regions.

Abstract: A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Abstract: A package for integrated circuit dies is disclosed comprising a ceramic base capable of having an integrated circuit die mounted to a central portion of one surface thereof to provide heat dissipation for the die; a lead frame with a central opening secured to the periphery of the same surface of the ceramic base; a raised frame member secured to both the lead frame and the peripheral portions of the same surface of the ceramic base exposed between the leads on the lead frame; a die mounted to the exposed central portion of the surface of the ceramic base surrounded by the lead frame and the raised frame member, and electrically bonded to leads on the lead frame; and a plastic potting material over and around the edges of the integrated circuit die and in contact with the exposed portion of the surface of the ceramic base adjacent the die, portions of the lead frame; and inner portions of the raised frame member to thereby encapsulate the integrated circuit die.

Abstract: Extremely high aspect ratio vertical walls may be constructed using sodium hydroxide etches of (100) orientation silicon. Mask bodies 18a, 18b and 18c are used to form vertical wall sections 20a, 20b and 20c from a silicon substrate 10.

Abstract: An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure.

Abstract: A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step. This thin nitride layer is, however, insufficiently thick to serve as a field implant mask in a subsequent field implant step. An additional low temperature oxide (LTO) layer is therefore provided over the nitride layer in the active area. The field implant step is then performed using the base oxide, the thin nitride, and the overlying LTO as a field implant mask. The boundaries of the overlying LTO define a field implant boundary. After the field implant step but before the field oxidation step, the LTO layer is removed from the top of the thin nitride layer. As a result, only the base oxide and the thin nitride layer is disposed over the active area during field oxidation.