Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.

Abstract: An information handling system includes a processor complex and a baseboard management controller (BMC). The processor complex provides boot status information in response to a system boot process of the processor complex. The BMC receives first boot status information from the processor complex in response to a first system boot process, compares the first boot status information to baseline status information to determine first boot status difference information, compares the first boot status difference information to baseline boot status difference information to determine that the information handling system experienced an anomaly during the first system boot process, and sends an alert that indicates that the first system boot process experienced the anomaly.

Abstract: An apparatus and method for mapping timer channels to protection groups. One embodiment of the method can be implemented in a microcontroller unit (MCU) that comprises a central processing unit (CPU) coupled to a plurality of timer channels and a plurality of programmable group output disable (PTGOD) circuits. The CPU can select a first group of the timer channels to respond to an assertion of a first output disable signal from a first of the PTGOD circuits. Each timer channel of the first group can disable an output signal in response to receiving the assertion of the first output disable signal.

Abstract: A control apparatus configured to control power of a device that communicates with a host system via a communication interface which complies with a predetermined standard includes a reception unit configured to receive a signal indicating that the host system transitions to a predetermined power state and a determination unit configured to determine, according to reception of the signal indicating that the host system transitions to the predetermined power state, a power state of each of the device and a physical layer of the communication interface used by the device from a plurality of power states, based on a power state of the host system, a power state of the device, and a power state of the physical layer of the communication interface included in the device and complying with the predetermined standard.

Abstract: An information processing system is capable of communicating with an external apparatus via a network. The information processing system is capable of operating in at least three operation modes including: a first mode; a second mode, which consumes less power than the first mode; and a third mode, which consumes less power than the second mode and where the communication via the network is not performed. The information processing system includes a mode control section and a second mode processing section. The mode control section, when the information processing system operates in the third mode, shifts the operation mode to the second mode periodically or in accordance with a predetermined time schedule. The second mode processing section performs a communication process via the network as information processing in the second mode.

Abstract: A storage device includes a first memory which stores data including activation data necessary to activate a host device, a second memory, and a controller which performs writing and reading operation of data stored in the first memory based on a request from the host device; acquires address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, reads data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmits the data stored in the second memory to the host device.

Abstract: A clock retiming circuit and method of operating a clock retiming circuit are described herein. A clock retiming circuit generates a retimed clock based on an input clock. The clock retiming circuit may have a normal mode when the input clock is available to the clock retiming circuit, and a retention mode that is entered in response to the input clock no longer being present. The clock retiming circuit resumes the normal mode in response to the clock again being present. The retention mode is a low current mode, in one aspect. Thus, the clock retiming circuit may operate in a low current mode when the input clock is not available. The clock retiming circuit may be tolerant to loss of the input clock. The clock retiming circuit may quickly re-establish the retimed clock in response to the input clock again becoming available.

Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.

Abstract: Embodiments of the present disclosure provide systems and/or methods for managing power distribution over a USB topology. In some embodiments, a host device is coupled to an upstream facing port device (UFP device) via a USB compliant connection, and a USB device is coupled to a downstream facing port device (DFP device) via a USB compliant connection. The UFP device and DFP device are connected via a non-USB compliant extension medium. In various embodiments, the UFP device and DFP device may be individually powered by different types of sources (such as external power sources, power distributed over the extension medium, batteries, USB bus power, and/or the like). The UFP device and DFP device cooperate to provide USB power distribution functionality throughout the USB topology despite the presence of the non-USB compliant extension medium.

Abstract: An example computing device includes a battery to power the computing device, a first operating system (OS), a second OS, and a hypervisor. The hypervisor is to: monitor a parameter of the first OS related to power to be drawn by the computing device for the first OS to enter a hibernate state; monitor a parameter of the second OS related to power to be drawn by the computing device for the second OS to enter the hibernate state; set a first modified remaining battery capacity of the first OS based on an actual remaining battery capacity of the battery and the parameter of the first OS; and set a second modified remaining battery capacity of the second OS based on the actual remaining battery capacity and the parameter of the second OS.

Abstract: Aspects of the present disclosure relate to providing a booting key to a remote system. A policy server receives a verification that a predetermined number of user devices provided secret information for booting a remote system. The policy server provides, in response to the received verification, a message for a key server to provide a booting key to the remote system, the key server providing the booting key in response to the message and causing the remote system to complete a booting procedure, in response to the message from the policy server.

Abstract: An active noise cancelling power supply to perform active noise cancelling of input power with noise to output power. The active noise cancelling power supply having a power transformation device receiving input power and converting the power to a voltage signal with a ripple. The active noise cancelling power supply has a ripple measuring device, which measures the ripple as the voltage signal with a ripple passes through the ripple measuring device producing a ripple signal. A controller with a data storage in communication with a processor, wherein computer instructions in the data storage are configured to instruct the processor to produce a first noise cancellation signal in volts or millivolts out of phase with the ripple signal and inject the first noise cancellation signal on the voltage signal with a ripple at a node forming a clean signal as output power.

Abstract: A Z-Wave networking device is disclosed having a processor, a WiFi transceiver, a Z-Wave network transceiver, and a flash memory from which the processor boots a startup image. The processor can boot a first startup image that configures the Z-Wave network transceiver as a Z-Wave network controller, and the processor can boot a second startup image that configures the Z-Wave network transceiver as a Z-Wave repeater node. An Internet server receives registration information for the device, and instructs the device to boot from the first startup image upon determining that a Z-Wave network controller is not present in the Z-Wave network, or from the second startup image upon determining that a Z-Wave network controller is already present in the Z-Wave network. In embodiments, the Z-Wave networking device comprises an HVAC thermostat.

Abstract: An electronic device includes an authentication unit that performs authentication to determine whether a power supply apparatus connected to the electronic device is a predetermined apparatus, a selection unit that makes a user select whether to use the power supply apparatus, when the authentication has failed, a storage unit that stores information indicating that the authentication has succeeded or the user has selected to use the power supply apparatus as history information. When the power supply apparatus is detached from the electronic device, the history information is deleted from the storage unit. The electronic device permits use of the power supply apparatus connected to the electronic device when the history information is stored in the storage unit while the electronic device is in a power ON state.

Abstract: The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles.

Abstract: A system includes hardware logic circuit configured to execute power control software. The hardware logic circuit executes the power control software to receive a request from a processing unit for delivery of a power level corresponding to a first power state and determine that the processing unit should operate at a second power state, where the second power state is different than the requested first power state. The hardware logic circuit also executes the power control software to cause a power supply to deliver a power level corresponding to the second power state to the processing unit.

Abstract: A system of the present invention includes: a storage unit configured to store the value of consumed energy of an information processing device configured to be supplied with power by a power supply device and a power storage device charged by the power supply device; and a calculation unit configured to calculate a power supply device upper limit value set as the upper limit value of a value representing a characteristic of energy supplied from the power supply device to the information processing device. The calculation unit is configured to calculate the power supply device upper limit value on the basis of the consumed energy in a predetermined period.

Abstract: Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memory elements. Based on this reported information, a controller ascertains an appropriate power level to insure a proper data retention voltage (DRV) is applied on voltage rails by a power management unit (PMU) circuit. By using the proper DRV based on the speed characteristics of the sub-elements within the memory elements, power conservation is achieved.

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.