Abstract: A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.

Abstract: A PSE includes a PSE controller that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs, via a switch, if certain conditions are met. Two different levels of currents are supplied to different terminals of the PSE controller that are connected to the data wire pairs and the spare wire pairs, and the resulting voltages are measured. The voltages are used to determine the PD impedances at the ends of the data wire pairs and spare wire pairs to determine whether a PD is connected to the data wire pair, whether another PD is connected to the spare wire pair, or whether a single PD is connected to both the data wire pairs and the spare wire pairs.

Abstract: A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.

Abstract: A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.

Abstract: A signal processing device includes a detection unit configured to detect an intent to use the signal processing device based on whether the signal processing device is in contact with a subject; and a power supply unit configured to supply power to operate the signal processing device based on the detected intent to use the signal processing device without using a separate ON/OFF switch to supply the power to operate the signal processing device.

Abstract: Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing power off commands. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first power off command for a data transaction purpose, and sends the first power off command to the host computer to initiate a data transaction. The OS, in response to the first power off command, calls an Advanced Configuration and Power Interface (ACPI) Machine Language (AML) code, which execute a system management interface (SMI) handler at the CPU to enter a system management mode (SMM). The SMI handler then sends a notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.

Abstract: Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first system management interface (SMI) message, and sends the first SMI message to the host computer to initiate a data transaction. The OS, in response to the first SMI message, execute a SMI handler in a system management random access memory (SMRAM) area at the CPU to enter a system management mode (SMM). The SMI handler then sends the notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.

Abstract: A relaying device for relaying serial communication that couples an upper level device and a power supply controller, the relaying device includes: a control information transmitter configured to, in response to receiving control information that is output from the upper level device to the power supply controller, transmit the control information, the control information being associated with power control; and a monitoring and controlling unit configured to monitor and control a control value to be transmitted to the power supply controller based on the control information transmitted from the control information transmitter.

Abstract: A watchdog function is performed for those messages which are used by a controller in a CAN bus to keep the other controllers active. All emitted keep-active messages are read again by the emitting controller itself and are checked for the presence of a reason. In the absence of such a reason, a restart is carried out.

Abstract: An embedded controller for power-saving and a method thereof are provided. The embedded controller is used for executing a plurality of tasks and includes a timer module and a control unit. The timer module includes a plurality of timers, and each of timers is corresponding to one of the tasks respectively. The control unit is coupled to the timer module and respectively sets a wake-up period according to each task. When the wake-up period of each timer is expired, each timer respectively generates a wake-up signal to the control unit. The control unit controls the embedded controller to transfer to an active model from an idle model according to the wake-up signals respectively. After executing the tasks corresponding to the wake-up signals respectively, the control unit controls the embedded controller to transfer to the idle model from the active model.

Abstract: An information processing apparatus includes a processor that is capable of switching a performance level to one of a plurality of performance levels with different power consumption, and a storage unit that stores a program for controlling the performance level of the processor. The processor executing the program detects the periodicity of load variation of the information processing apparatus, and changes, according to the periodicity of the load variation, a determination interval for determining whether to switch the performance level of the processor.

Abstract: In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.

Abstract: Bootability of a computer system with multiple LUNs. A flash device powers-on into a default LUN, from which the system boots, maintaining any other LUNs unavailable. The first LUN reconfigures the system to remove itself as the available LUN, to load a second LUN as the only available LUN, and to reboot the computer system into the newly available second LUN. The second LUN reconfigures the system to load any additional LUNs, such as removable storage on the flash drive. Upon reconfiguration, the system includes multiple LUNs. The second LUN includes an interpolated LUN driver, which exposes additional LUNs before operation of other device drivers. The interpolated LUN driver takes control during boot-up, exposing any available LUNs before the regular environment's operating system.

Abstract: A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a power adapter via a narrow-voltage direct current/direct current (NVDC) charger and from the power supply. The method also includes, in response to the detection, disabling a dynamic power management function of the NVDC charger. The method further includes monitoring input current or input power provided to the powered device by the NVDC charger and determining if the input current or input power exceeds a threshold. In addition, the method includes, if the input current or input power exceeds the threshold, triggering a throttling of an operating clock frequency of the powered device. The method could also include (i) disabling a specified mode of operation and turning on a voltage regulator of the NVDC charger in response to the detection and (ii) providing over-voltage protection.

Abstract: The described embodiments comprise a first hardware context. The first hardware context receives, from a second hardware context, an indication of a memory location and a condition to be met by the memory location. The first hardware context then sends a signal to the second hardware context when the memory location meets the condition.

Abstract: A power management method for use in an electronic system is provided. The electronic system has a processor and a power management unit. The method has the steps of: when the processor has entered a low power state and an awakening event occurs, calculating a staying time from the time point the processor enters the low power state till the time point the awakening event occurs, wherein the operation voltage of the processor is at a first voltage level in the low power state; and when the processing starts to exit the low power state according to the awakening event, determining a wait time, during which the operation voltage of the processor is recovered to a second voltage level of a working state from the first voltage level, wherein the first voltage level is lower than the second voltage level.

Abstract: Methods, systems, and devices are described for managing power consumption in a modem of a mobile device. A receive power associated with a receiver of the modem may be measured during a scheduled power-up of the modem associated with checking for paging messages. A power consumption metric associated with transmitting a pending wireless data transaction at a transmitter of the modem may then be estimated based on the measured receive power associated with the receiver. A determination of whether to transmit the pending wireless data transaction at a first time may then be made based at least in part on the estimated power consumption metric.

Abstract: A circuit system includes: a plurality of memory blocks; a power supply circuit configured to supply operating power and substrate power to the plurality of memory blocks; a plurality of first power supply switches configured to control whether or not the operating power is supplied from the power supply circuit to the plurality of memory blocks; and a control circuit configured to control the power supply circuit and the plurality of first power supply switches, wherein the control circuit changes a voltage of the operating power to be supplied by the power supply circuit and a voltage of the substrate power to be supplied by the power supply circuit, based on a state of whether the first power supply switches are in a supplying state or a blocking state.

Abstract: A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal. The frequency signal and the phase signal that have passed through a filter are transmitted to the oscillator to generate the reference signal for generating a clock signal. The sampling circuit generates an input data signal according to the reference signal. The transmitter circuit modulates an output data signal according to the clock signal to generate and transmit an output signal to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission stand.

Abstract: Examples are disclosed for remotely initializing or booting a client or host device. In some examples, a network (NW) input/output (I/O) device coupled to a host device connects to a remote server via a NW communication link. For these examples, modules of the network I/O device establishes a control path to a non-volatile memory express (NVMe) controller maintained at the remote server using a remote direct memory access (RDMA) protocol. Properties of a storage device controlled by the NVMe controller have an RDMA service tag (STag) to indicate accessible allocated portions of the storage device. A system basic I/O system (BIOS) is capable of using the RDMA STag to access the storage device and load an operating system (OS) kernel. Also, one or more device drivers can remotely boot the host device using the RDMA STag.