Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

Abstract: In one example, a computer having a processor and a byte-addressable non-volatile read-write main memory. The memory is partitioned into plural regions, each region having at least one defined operational property. At least one of the regions is a metadata region to store plural data sets. Each data set specifies a location in memory, and the at least one operational property, of a corresponding one of the regions.

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Abstract: Systems and methods may be used to securely booting multiple devices. A method may include initiating a boot sequence at a first device in an array of devices, booting a first distributed boot executive (DBE) on the first device, updating a Platform Configuration Register (PCR) with a first boot measurement, sharing the first boot measurement with a second DBE on a second device of the devices before booting a next boot step at the first device, receiving a second boot measurement from the second DBE, and booting the first device into a next boot stage in response to receiving the second boot measurement from the second DBE.

Abstract: An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.

Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

Abstract: An information processing apparatus comprises: a power control unit that, when the information processing apparatus operates in a first power mode, controls to supply power to both a first control unit and a second control unit, and when the information processing apparatus operates in a second power mode in which a power consumption is smaller than that in the first power mode, controls to supply power to the second control unit, wherein when the information processing apparatus operates in the second power mode, the second control unit can respond to a status request of a first type in which specific identification information is designated and a status request of a second type in which specific identification information is designated while maintaining the second power mode.

Abstract: Technologies for hybrid sleep power management include a computing device with a processor supporting a low-power idle state. In a pre-boot firmware environment, the computing device reserves a memory block for firmware use and copies platform wake code to a secure memory location, such as system management RAM (SMRAM). At runtime, an operating system may execute with the processor in protected mode. In response to a request to enter a sleep or suspend state, the computing device generates a system management interrupt (SMI). In an SMI handler, the computing device copies the wake code from SMRAM to the reserved memory block. The computing device resumes from the SMI handler to the wake code with the processor in real mode. The wake code enters the low-power idle state and then jumps to a wake vector of the operating system after receiving a wake event. Other embodiments are described and claimed.

Abstract: Cooling of at least two heat generating electronic components of a computing device is described herein. The computing device includes the at least two heat generating electronic components. The at least two heat generating electronic components includes a first heat generating electronic component and a second heat generating electronic component. The first heat generating electronic component and the second heat generating electronic component are in thermal communication. The computing device also includes a first sensor operable to measure a first temperature. The first temperature is associated with the first heat generating electronic component.

Abstract: A power system includes a voltage detection IC which outputs a reset signal to a microcomputer when an input voltage is equal to or lower than a reset release voltage, releases outputting of the reset signal when the input voltage exceeds the reset release voltage, and outputs the reset signal to the microcomputer again after the input voltage exceeds the reset release voltage when the input voltage is equal to or lower than a reset detection voltage which is lower than the reset release voltage and a voltage conversion circuit which sets a first voltage associated with a change of a power voltage as the input voltage before start of operation of the microcomputer and sets a second voltage which is associated with a change of the power voltage and is lower than the first voltage as the input voltage after the start of operation the microcomputer.

Abstract: A startup sequence in a computer system is initiated by detecting a bus reset event in an I/O device connected to a host, and responsively to the bus reset event communicating resources required to be allocated by the host. When a startup command from a host driver is not received within a predetermined bus reset count, the device autonomously changes its current configuration to a safe mode configuration, wherein fewer resources are required to be allocated relative to the current configuration. The safe mode configuration is communicated from the device to the host.

Abstract: A managed boot process system includes a management device coupled to a networking device through a network. The networking device includes a storage system with an assured boot image, a plurality of runtime images, and a plurality of session data, and a memory system having boot instructions. A processing system in the networking device stores the plurality of session details in the storage system during a management session with the management device and prior to a reboot. The processing system then performs a reboot and executes the boot instructions to load the assured boot image. The networking device then uses the session details to restart the management session without reauthorization subsequent to loading the assured boot image and prior to loading a runtime image. The networking device then provides a graphical user interface over the network to the management device and uses it to receive a management instruction for execution.

Abstract: A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.

Abstract: One embodiment pertains to a method including determining the duty cycle of a PWM signal, operating in valley current control mode when the duty cycle is greater than fifty percent, operating in peak current control mode when the duty cycle is less than fifty percent, and including, commencing a PWM pulse upon the occurrence of a pulse of a first clock signal pulse, and terminating the PWM pulse upon a level of a signal exceeding a positive window threshold.

Abstract: Example embodiments disclosed herein relate to reporting a first updated threshold level related to a battery. A parameter related to power to be drawn by the computing device for the first OS to enter a hibernate state is monitored. The first updated threshold level are set based on the parameter. The first updated threshold level is reported to the first OS. The first OS is to vary the first battery level threshold based on the first updated threshold level.

Abstract: A circuit for transmitting data in an integrated circuit device is described. The circuit comprises a first data width conversion circuit configured to receive a first portion of transmit data to be transmitted in parallel; a first parallel-in, serial-out circuit configured to receive an output of the first data width conversion circuit; a first reset timer configured to provide a first reset signal to enable resetting the first data width conversion circuit; a second data width conversion circuit configured to receive a second portion of the transmit data; a second parallel-in, serial-out circuit configured to receive an output of the second data width conversion circuit; and a second reset timer configured to provide a second reset signal to enable resetting the second data width conversion circuit.

Abstract: Provided is a technique to enhance security of a computer in a multi-OS operating environment. A memory image of a primary OS is in an active state, and a memory image of a secondary OS is in a non-active state. When switching is performed from the primary OS to the secondary OS, a runtime image is created, and a digest P is calculated and encrypted (C). When switching is performed from the secondary OS to the primary OS, a digest of the stopped runtime image is calculated. Only when comparison between the decrypted digest P and the calculated digest shows agreement, is switching of the primary OS allowed.

Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.