Patents Examined by Brian K. Young
  • Patent number: 11115045
    Abstract: A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between an analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 7, 2021
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Lars R. Furenlid, Maria Ruiz-Gonzalez
  • Patent number: 11108405
    Abstract: A device for compressing first data which are to be compressed comprises a control unit configured to compress the first data based upon further data to obtain compressed data. The control unit is configured to provide memory area information indicative of a memory location of the further data.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 31, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Claudia Meitinger, Roland Ebrecht, Peter Huewe
  • Patent number: 11101813
    Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 24, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Sicurella, Manuela La Rosa
  • Patent number: 11101817
    Abstract: A transcoder is disclosed. The transcoder may comprise a buffer to store input encoded data. An index mapper may map an input dictionary to an output dictionary. A current encode buffer may store a modified current encoded data, which may be responsive to the input encoded data, the input dictionary, and the map from the input dictionary to the output dictionary. A previous encode buffer may store a modified previous encoded data, which may be responsive to the input encoded data, the input dictionary, and the map from the input dictionary to the output dictionary. A rule evaluator may generate an output stream responsive to the modified current encoded data in the current encode buffer, the modified previous encoded data in the previous encode buffer, and transcoding rules.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 24, 2021
    Inventors: Yang Seok Ki, Ho Bin Lee
  • Patent number: 11100389
    Abstract: A digital signal may be converted into a spiking analog signal. A different constant current may be applied to each of a plurality of switch circuits. Each bit of the digital signal may be applied to a corresponding one of the plurality of switch circuits. Each switch circuit may apply the corresponding constant current to a common output when the corresponding bit has a predetermined value. Each switch circuit may not apply the corresponding constant current to the common output when the corresponding bit does not have the predetermined value. A common current may be applied at the common output to a spiking neuron circuit.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 24, 2021
    Assignee: ELECTRONIC WARFARE ASSOCIATES, INC.
    Inventors: Dirk Niggemeyer, Lester A. Foster, III
  • Patent number: 11095302
    Abstract: A frequency delta sigma modulation signal output circuit includes a phase modulation circuit that outputs a phase modulation signal based on a delay signal obtained by delaying a signal to be measured, in synchronization with the signal to be measured, and a frequency ratio digital conversion circuit that generates a frequency delta sigma modulation signal using a reference signal and the phase modulation signal.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 17, 2021
    Inventor: Masayoshi Todorokihara
  • Patent number: 11088699
    Abstract: An electronic device includes a bandgap reference circuit having an output, and a bias input; a piecewise compensation circuit having an output coupled to the bias input, and an input; and a piecewise compensation current generator having an output coupled to the input of the piecewise compensation circuit, and a knee point temperature adjustment circuit coupled to the output of the piecewise compensation current generator.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tallam Vishwanath, Sandeep Shylaja Krishnan
  • Patent number: 11088703
    Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 10, 2021
    Assignee: Jariet Technologies, Inc.
    Inventors: Ark-Chew Wong, Richard Dennis Alexander
  • Patent number: 11082057
    Abstract: An apparatus such as an electronic circuit includes an input operable to receive an input signal; a dynamic common mode adjustor operable to: i) derive a differential signal from the received input signal, and ii) control an offset of the differential signal as a function of the received input signal to produce an offset differential signal; and an output operable to output the offset differential signal. In one arrangement, the offset differential signal outputted from the output includes a first signal and a second signal; a difference between the second signal and the first signal proportionally varies with respect to the received input signal.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Holm Hansen, Mikkel Hoyerby
  • Patent number: 11075437
    Abstract: A mounting bracket for an antenna information sensor unit includes a main horizontal arm, a first clamping member, and a second clamping member. The main horizontal arm is separately connected to the first clamping member and the second clamping member, and a distance between the first clamping member and the second clamping member is adjustable. The first clamping member and the second clamping member are configured to fasten the main horizontal arm on the top of an antenna, and the main horizontal arm is configured to connect to the antenna information sensor unit.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: July 27, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fangqing Duan, Mingyan Ning, Zhiming Yang, Hu Zhao, Meng Chen, Zhuolin Cai, Xin Feng
  • Patent number: 11075621
    Abstract: A delay circuit includes a state transition section configured to start state transition based on a trigger signal and output state information indicating the internal state and a transition-state acquisition section configured to latch and hold the state information. The state transition section includes a tapped delay line in which a plurality of delay elements are coupled, a logical circuit configured to generate a third signal based on a first signal based on the trigger signal and a second signal, which is an output signal of the delay element, and a synchronous transition section configured to count an edge of the third signal. The state information is having an output signal of the synchronous transition section and an output signal of the tapped delay line. A humming distance of the state information before and after the state transition is 1.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 27, 2021
    Inventor: Masayoshi Todorokihara
  • Patent number: 11070221
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines maximum value signals, to which the second quantized outputs correspond in a predetermined interval, and averages the maximum value signals to generate a reference signal, and compares the reference signal with each of the maximum value signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: July 20, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Ting-Hao Wang, Hsin-Han Han, Yu-Chu Chen
  • Patent number: 11070220
    Abstract: The value range for which an error in a digital signal can be corrected is expanded. A control unit generates characteristic information indicating the relationship between an input and an output of an A/D converter and sets a value range. The control unit, in a case in which a value indicated by a first digital signal obtained by the A/D converter converting a first analog voltage signal is within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of the first digital signal and characteristic information, and in a case in which a value indicated by the first digital signal is not within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of a second digital signal obtained by the A/D converter converting the second analog voltage signal and characteristic information.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: July 20, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Atsushi Miki
  • Patent number: 11057048
    Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Vincent Quiquempoix
  • Patent number: 11057047
    Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Vincent Quiquempoix, Zeynep Sueda Turk
  • Patent number: 11057042
    Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: July 6, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Chieh Yang, Shih-Hsiung Huang, Liang-Huan Lei
  • Patent number: 11043958
    Abstract: A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 22, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu
  • Patent number: 11031948
    Abstract: A diagnostic system includes a detection circuit comprising a first impedance, a second impedance, a first input pin, a second input pin, a first output pin and a second output pin. The detection circuit is configured to receive an input signal via the first and the second input pins. The first impedance is configured to electrically couple the first input pin and the first output pin, and the second impedance is configured to electrically couple the first input pin with the second input pin and second output pin. The diagnostic system also includes a communication channel. The diagnostic system further includes an input circuit comprising a third input pin, a fourth input pin and a third output pin. The input circuit is configured to provide, via the third output pin, a voltage signal.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 8, 2021
    Assignee: BAKER HUGHES OILFIELD OPERATIONS LLC
    Inventors: Lifeng Wang, Hao Wang, Zhili Zhou, Xiaoyan Huang, Ran Ao
  • Patent number: 11025262
    Abstract: The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)th pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to ?1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ith pipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ith pipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 1, 2021
    Inventors: Yuanjun Cen, Xing Zhu, Jinda Yang
  • Patent number: 11018688
    Abstract: A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chengkai Guo, Wanghua Wu