Abstract: A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.

Abstract: A diagnostic system includes a detection circuit comprising a first impedance, a second impedance, a first input pin, a second input pin, a first output pin and a second output pin. The detection circuit is configured to receive an input signal via the first and the second input pins. The first impedance is configured to electrically couple the first input pin and the first output pin, and the second impedance is configured to electrically couple the first input pin with the second input pin and second output pin. The diagnostic system also includes a communication channel. The diagnostic system further includes an input circuit comprising a third input pin, a fourth input pin and a third output pin. The input circuit is configured to provide, via the third output pin, a voltage signal.

Abstract: The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)th pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to ?1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ith pipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ith pipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), at least one conversion circuit, and at least one amplifier such that a number of conversion circuits and a number of amplifiers is less than a number of DACs. Each DAC is configured to receive an analog input signal in non-overlapping durations of a clock signal and generate a corresponding analog output signal. At least one of the conversion circuits is coupled with at least two DACs, and each conversion circuit is configured to perform conversion operation on a corresponding analog output signal to generate digital signals. At least one of the amplifiers is coupled with at least two DACs, and each amplifier is configured to perform amplification operation on a corresponding analog output signal.

Abstract: A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.

Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.

Abstract: A collimator for under-display fingerprint sensing includes (a) a substrate having opposite facing first and second sides, (b) an array of microlenses disposed on the first surface for focusing light from a fingerprint surface onto a focal plane that is between the array of microlenses and the second side of the substrate such that the light, as projected by the array of microlenses, is diverging when exiting the second side of the substrate, and (c) an array of apertures between the array of microlenses and the substrate, wherein each of the apertures is aligned to and cooperates with a respective one of the microlenses to form a field-of-view-limited lens having a field of view corresponding to a respective local portion of the fingerprint surface.

Abstract: A first value of a first data element in a first set of data elements is obtained, the first set of data elements being based on a first time sample of a signal. A second value of a second data element in a second set of data elements is obtained, the second set of data elements being based on a second, later time sample of the signal. A measure of similarity is derived between the first value and the second value. Based on the derived measure, a quantisation parameter useable in performing quantisation on data based on the first time sample of the signal is determined. Output data is generated using the quantisation parameter.

Abstract: A voltage-to-time-to-digital converter (VTDC) and conversion method are provided using a coarse analog-to-digital converter (ADC). A voltage-to-time converter (VTC) receives an analog input voltage-differential signal with a first time duration and supplies an analog first time-differential signal. An ADC receives the input voltage-differential signal and supplies a first digital code representing m bit values. A time-to-digital converter (TDC) receives a second time-differential signal with a second time duration derived from the first time duration. The TDC supplies an output digital code representing p bit values, where p>m. In one aspect the first digital code programs an initial set of TDC residue generators. In another aspect, a dither circuit controls the second time duration in response to a pseudo random signal combined with the first digital code.

Abstract: A wideband dual polarized antenna array system, with minimal number of RF ports that enables wideband array frequency ratios of 25:1 to 120:1. Reduced grating lobe performance is enabled by employing antennas-within-antennas. Orientation and spacing of antennas in novel methodologies further reduces sidelobes and grating lobes. Finally, this technology reduces the number of RF ports, compared to Tightly Coupled Dipole Antenna (TCDA) arrays by 10× to 25× times.

Abstract: An in-situ delay measurement is performed for an envelope-tracking power amplifier of an RF input signal. Because the delay measurement is in-situ, the delay measurement avoids the necessity to down convert and digitize a version of an RF output signal from the envelope-tracking power amplifier.

Abstract: This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.

Abstract: A class-D amplifier includes an analog-to-digital converter (ADC) configured to generate a first digital signal based on an analog input signal and a feedback signal received at an input node. A loop filter is configured to modify the first digital signal by moving an error of the ADC out of a predetermined frequency band, and a compensation filter is configured to further modify the first digital signal by introducing one or more poles or zeros, thereby generating a second digital signal. An output circuit is configured to generate an output signal at an output node based on the second digital signal, and the feedback signal is generated from the output signal.

Abstract: There is provided a time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal with respect to the reference signal, the time to digital converter including a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information acquired by the transition-state acquiring section, the time digital value corresponding to a number of times of transition of the internal state.

Abstract: Devices and techniques are generally described for compression of natural language processing models. A first index value to a first address of a weight table may be stored in a hash table. The first address may store a first weight associated with a first feature of a natural language processing model. A second index value to a second address of the weight table may be stored in the hash table. The second address may store a second weight associated with a second feature of the natural language processing model. A first code associated with the first feature and comprising a first number of bits may be generated. A second code may be generated associated with the second feature and comprising a second number of bits greater than the first number of bits based on a magnitude of the second weight being greater than a magnitude of the first weight.

Abstract: A multi-symbol per stage pipelined time-to-digital converter (TDC) is presented. The TDC includes a quantizer and a residue generator. The quantizer has an input to accept an analog input first time-differential signal comprising a binary level first edge separated from a binary level second edge by a first duration of time. The first time-differential signal is capable as being represented by m time intervals. The quantizer has an output to supply a first digital code representing Ceil(log2(m)) bit values responsive to (m?1) time interval measurements. The first digital code is a time-to-digital conversion. For example, if the first time-differential signal is capable of being represented as a p-bit binary coded digital word, the quantizer outputs a first digital code representing the Ceil(log2(m)) most significant bit (MSB) values of the p-bit digital word.

Abstract: The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain.

Abstract: Sampler circuitry including load circuitry having sampler switches to sample first and second load currents, the load circuitry having first and second load nodes and a biasing node; a power supply node connected to a voltage source; a first current path extending from the power supply node to the first load node to provide the first load current at the first load node, where a first supply-connection impedance is connected along the first current path; a second current path extending, in parallel with the first current path, from the power supply node to the second load node to provide the second load current at the second load node for use by the load circuitry, where a second supply-connection impedance is connected along the second current path between the power supply node and the second load node; first and second input-connection impedances; and control circuitry.

Abstract: A digital-to-analog converter includes a resistor ladder, a first switch and a protection circuit. The first switch includes a first terminal and a second terminal that are respectively coupled to a rung of the resistor ladder and a reference voltage node. The protection circuit is coupled to the reference voltage node and to a reference voltage input terminal. The protection circuit includes a second switch, a third switch, and a fourth switch. First and second terminals of the second switch are respectively coupled to the reference voltage node and the reference voltage input terminal. First and second terminals of the third switch are respectively coupled to the reference voltage node and a reference voltage feedback terminal. The first and second terminals of the fourth switch are respectively coupled to the reference voltage input terminal and the reference voltage feedback terminal.