Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

Abstract: Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.

Abstract: Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

Abstract: Apparatus and associated methods relate to providing a regulation loop using a digital representation of a loop error signal along with a flexible multiplying capacitive digital-to-analog converter (MC-DAC) circuit to control one or more power switches (e.g., transistors) delivering required power (including voltage and/or current) to a load circuit. In an illustrative example, the MC-DAC circuit may include a digital-to-analog converter (DAC) configured to selectively couple to two different reference voltages in response to switch control signals generated by a digital filter. A capacitive level shifter may be coupled to the output of the DAC. A re-sampling circuit may be coupled to the output of the capacitive level shifter to generate a gate control signal to control the one or more power switches. The regulation loop may advantageously generate the gate control signal using a substantially reduced die area.

Abstract: A compressor, an adder circuit, and an operation method thereof are provided. The compressor includes a first adder circuit and a second adder circuit. The first adder circuit receives a plurality of input values. The first adder circuit outputs a first inverted sum value (an inverted signal of a sum value) and a first inverted carry value (an inverted signal of a carry value). One of a plurality of input terminals of the second adder circuit is coupled to the first adder circuit to receive one of the first inverted sum value and the first inverted carry value. The second adder circuit outputs a second inverted sum value and a second inverted carry value.

Abstract: A system for analog-to-digital conversion, preferably including one or more optical inputs, optical sources, phase remodulators, and/or photonic circuits, and optionally including detector banks and/or digital electronics. A method for analog-to-digital conversion, preferably including receiving an optical input signal, generating a phase-modulated optical signal, and/or generating a plurality of optical outputs, and optionally including generating a plurality of electrical outputs and/or encoding a digital representation of the outputs.

Abstract: There is provided a successive-approximation type AD converter and a pipeline type AD converter without delay due to sample hold. A successive-approximation type AD converter 1 includes: receiving circuits configured to output the analog input signal according to the received analog input signal; subtractors configured to calculate subtraction signals between the analog input signal in each of n successive conversions and comparison signals obtained by DA-converting the control values by DA converters; comparators configured to determine a high-low relationship between the voltages of the subtraction signals and the reference voltage; a control circuit configured to update the control values so that the comparison signals approach the analog input signal based on the comparison results; and an output register configured to output the digital output signal based on the comparison results of the comparators.

Abstract: In one example, an apparatus comprises: a comparator; a sampling capacitor having a first plate and a second plate. The first plate is coupled with an output of a charge sensing unit that senses charge generated by a photodiode, whereas the second plate is coupled with an input of the comparator. The apparatus further includes a controller configured to: at a first time, set a first voltage across the sampling capacitor based on an output voltage of the charge sensing unit; reset the charge sensing unit to set the first plate at a second voltage and to set the second plate at a third voltage based on the first voltage and the second voltage; compare, using the comparator, the third voltage against one or more thresholds; and generate, based on the comparison result, a quantization result of the output voltage of the charge sensing unit at the first time.

Abstract: An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Abstract: Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.

Abstract: A signal transmission device for pulse density modulated signals comprises a signal input for an input signal with a defined maximum signal value, a modulation stage for generating a pulse density modulated transmission signal out of the input signal, a locking device at the input for the pulse density modulated transmission signal to overwrite same with a static fault signal, a pulse reconstructing transmission path for the pulse density modulated transmission signal, a demodulation stage at the output, for reconstructing the input signal out of the transmitted pulse density modulated transmission signal, and a signal change monitoring device capturing the pulse density modulated transmission signal of the transmission path at the output, which has an error signal output for signaling the detection of a missing dynamic pulse density modulated transmission signal on the transmission path due to the static fault signal.

Abstract: A digital to analog converter, a method for driving the same, and a display device are provided. The digital to analog converter includes: a first resistor string, 2m first multiplexers, a first voltage selector, a second resistor string, a second voltage selector, and a second multiplexer, where the 2m first multiplexers, the first voltage selector, and the second voltage selector operate in cooperation with each other so that the entire second resistor string can be connected in series to the first resistor string for further division.

Abstract: Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e.

Abstract: A polar-code based encoder is used to perform a transfer of useful data to a polar-code based decoder via a Binary Discrete-input Memory-less Channel. The Divide and Conquer structure consists of a multiplexer having useful data bits and a set of frozen bits as inputs followed by a polarization block of size N=2L, wherein the polarization block of size N comprises a set of front kernels followed by a shuffler and two complementary polarization sub-blocks of size N/2 with a similar structure as the polarization block of size N but with half its size. A dynamically configurable interleaver is present between the shuffler and one and/or the other of the complementary polarization sub-blocks at each recursion of the Divide and Conquer structure. The configuration of the dynamically configurable interleavers is dynamically modified according to changes detected in the Binary Discrete-input Memory-less Channel.

Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

Abstract: An information processing method includes obtaining text information and a sentence set; encoding a sentence in the sentence set using a first encoder to obtain a first encoded vector, and encoding the sentence using a second encoder to obtain a second encoded vector. The first encoded vector is determined according to the sentence, and the second encoded vector is determined according to a feature of the sentence. The method also includes determining a sentence encoded vector according to the first and second encoded vectors; encoding the sentence encoded vector using a third encoder to obtain global information; decoding the global information using a decoder; and determining a probability value corresponding to the sentence. Accordingly, when a deep learning method is used, a manually extracted sentence is further added to perform feature training, to effectively improve a learning capability of a model, thereby improving an information processing capability and effect.

Abstract: According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.

Abstract: A field measuring device includes a sensor, a measuring transducer, and interface electronics. The interface electronics include a measuring and control device, and first and second terminals for connecting an external electrical device. A current controller and a current measuring device are connected in series in a terminal current path between the first and second terminals. The interface electronics has a voltage source that can be switched on in the terminal current path and disconnected from the terminal current path, so that the voltage source can drive a current in the terminal current path in the switched-on state and in the case of a connected external electrical device. The measuring and control device actuates and reads the current controller, the current measuring device, and the voltage source such that a current signal is output or input via the first and second terminals when an external device is connected.

Abstract: Systems and methods for sensing an analog signal through digital input/output (I/O) pins are provided. Aspects include an analog to digital (ADC) circuit configured to generate a digital signal based on observations of the analog signal obtained from an analog circuit, where the ADC circuit includes a difference amplifier, a comparator, a divideby2 counter and two AND gates. Aspects also include a controller including a pin configured to receive the digital signal. The controller is configured to count pulses within the digital signal and determine values corresponding to the analog signal based on the counted pulses.