Abstract: A multiplying digital to analog converter (MDAC) includes a first resistor configured to be selectively connected to a current output node based on a first bit of a first portion of an input digital code and a second resistor configured to be selectively connected to the current output node based on a second bit of the first portion of the input digital code. A resistance of the second resistor is a resistance of the first resistor scaled by a factor. The MDAC further includes a first capacitor configured to be selectively connected to the current output node based on the first bit of the first portion and a second capacitor configured to be selectively connected to the current output node based on the second bit of the first portion. A capacitance of the second capacitor is a capacitance of the first capacitor scaled by an inverse of the factor.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: A voltage-controlled ring oscillator (VCRO) and a VCRO-based sigma delta modulator having capability of enabling and disabling the VCRO cells. A VCRO includes a plurality of inverters coupled in a ring and a transition detector. The transition detector detects a transition of a first inverter and sends a control signal to enable a second inverter if the transition of the first inverter is detected. The transition detector may include a comparator configured to compare an input and an output of an inverter(s) to detect the transition of the first inverter and a latch configured to hold the control signal until it is reset.

Abstract: A method for compressing activation data of a neural network to be written to a storage is provided. The activation data is formed into a plurality of groups and a state indicator indicates whether there are any data elements within each group that have a non-zero value. A second state indicator indicates, for groups having a non-zero value, whether sub-groups within the group contain a data element having a non-zero value. A sub-group state indicator indicates, for each sub-group having a non-zero value, which data elements within that sub-group have a non-zero value. Non-zero values of data elements in the activation data are encoded and a compressed data set is formed comprising the first state indicators, any second state indicators, any sub-group state indicators and the encoded non-zero values.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.

Abstract: Systems, apparatus and methods are provided for compressing data. An exemplary method may comprise interleaving one or more literal length fields with one or more literal fields to an output. The literal fields may contain a first data segment literally copied to the output, and each of the one or more literal length fields may contain a value representing a length of a succeeding literal field. The method may further comprise determining a second data segment being matched to a previously literally copied sequence of data and a match position and writing to the output one or more match length fields and a match position field containing the match position. The literal length fields may contain a total length of the first data segment and the match length fields may contain a total length of the second data segment.

Abstract: A predictive model utilizes a set of coefficients for processing received input data. To reduce memory usage storing the coefficients, a compression circuit compresses the set of coefficients prior to storage by generating a cumulative count distribution of the coefficient values, and identifying a distribution function approximating the cumulative count distribution. Function parameters for the determined function are stored in a memory and used by a decompression circuit to apply the function the compressed coefficients to determine the decompressed component values. Storing the function parameters may consume less memory in comparison to storing a look-up table for decompression, and may reduce an amount of memory look-ups required during decompression.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code.

Abstract: Disclosed are techniques for encoding a set of sensor content symbols at least in part via applying a processing window of an adjustable size.

Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a program that make it possible to cope with an output of a PCM signal using one DSD signal. A distribution apparatus includes an extraction section that, in a case where a PCM signal having a predetermined sampling frequency is generated from a DSD signal, extracts a predetermined number of samples from the DSD signal around samples at a predetermined interval determined by the predetermined sampling frequency, and a filtering section that generates the PCM signal having the predetermined sampling frequency by filtering the extracted predetermined number of samples. The present technology is applicable to, for example, a distribution apparatus, etc., that distributes the PCM signal to a client apparatus.

Abstract: An antenna device includes a ground member including a plane part and a plurality of extension parts extending from one end of the plane part in a first direction and arranged along a second direction, a plurality of patch-type radiators arranged on the plane part along the second direction and configured to radiate vertical polarization, and a plurality of straight radiators spaced apart from the ground member, respectively arranged to be adjacent to the plurality of extension parts, extending in the first direction, and configured to radiate horizontal polarization.

Abstract: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

Abstract: A circuit for high accuracy element matching is provided. The circuit includes an analog to digital converter (ADC) configured to generate an output code. A current source is configured to provide a signal to the ADC. The current source includes a first current branch including a first unit element group having a first unit element coupled by way of a first set of switches to a first node and a second node and a second unit element coupled by way of a second set of switches to the first node and the second node. A second current branch includes a second unit element group having a third unit element coupled by way of a third set of switches to the first node and the second node and a fourth unit element coupled by way of a fourth set of switches to the first node and the second node. A control circuit is configured to provide control signals to the sets of switches based on the output code. The control circuit is further configured to sort unit element currents and to dynamically switch unit elements.

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) having a resistor network. The resistor network includes a first and second segments. The first segment includes a first switch coupled between a first supply voltage node and a first set of resistors. The second segment includes a second switch coupled between the first supply voltage node and a second set of resistors. The first segment includes a third switch coupled in series with a second resistor. The series-combination of the third switch and second resistor coupled in parallel with at least one resistor of the first set of resistors. The second segment includes a fourth switch coupled in series with a third resistor. The series-combination of the fourth switch and third resistor is coupled in parallel with at least one resistor of the second set of resistors.

Abstract: This disclosure provides an active envelope detector to generate an output voltage based on an input radio-frequency (RF) signal. The active envelope detector includes a plurality of transistors configured to operate in a sub-threshold mode and generate an output voltage based on the input RF signal. A delta-modulation analog-to-digital converter (ADC) and a sigma-delta modulation ADC are provided. Both ADCs include an implementation of the active envelope detector to receive input RF signals.

Abstract: Methods and systems to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a current mode digital-to-analog converter (DAC) configured to multiply an input signal with an input current to generate a signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the signal into at least a first current having a first amplitude and a second current having a second amplitude. The device can further include a mixer configured to multiply the second current with a clock signal to generate a third current. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

Abstract: Various implementations described herein are directed to device having multiple stages. The device may include a first stage that converts an analog voltage signal in a power supply domain into a digitally coded signal. The device may include a second stage that generates a derivative of the digitally coded signal, detects an event of the analog voltage signal based on the derivative of the digitally coded signal, and derives a control signal based on the event. The device may include a third stage that injects current into or sinks current from the power supply domain that is associated with the analog voltage signal based on the control signal.

Abstract: A readout circuit that includes an amplifier circuitry, an analog-to-digital converter, a feedback circuit and a control logic is introduced. The amplifier circuitry may receive and amplify a differential signal that is obtained according to an input signal and a feedback signal to generate an amplified signal. The analog-to-digital converter is configured to convert the amplified signal to generate a n-bit digital code, wherein n is a positive integer. The feedback circuit is configured to search and generate a m-bit digital code based on a value of the n-bit digital code and convert the m-bit digital code to generate the feedback signal, wherein m is a positive integer. The control logic is coupled to the analog-to-digital converter and the feedback circuit, and configured to control the analog-to-digital converter and the feedback circuit. A multi-bit digital output of the readout circuit is generated according to the n-bit digital code and the m-bit digital code.

Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Abstract: The invention discloses a calibration circuit and a calibration method for an analog-to-digital converter (ADC). The calibration method of the ADC includes the following steps: (a) resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (b) changing a terminal voltage of at least one capacitor in the first capacitor group; (c) the ADC generating a first digital code; (d) after the first digital code is obtained, resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (e) changing a terminal voltage of at least one capacitor in the third capacitor group; and (f) the ADC generating a second digital code. The first digital code and the second digital code are used to correct the output of the ADC.