Abstract: A field device commissioning system includes a commissioning tool, a communication module and an IO module. The commissioning tool is configured to communicate with a client in a plurality of communications. The commissioning tool is configured to perform a parallel execution of executing a plurality of loop processing logics that includes at least one input loop check or at least one output loop check in parallel for all of a plurality of channels which belongs to each slot in each unit, in accordance with the plurality of request for executions of loop checks from the client in the plurality of communications. The commissioning tool is configured to perform in series a plurality of the sequential executions for a plurality of the slots in each unit, wherein each execution including the plurality of loop processing logics. The commissioning tool may be configured to perform in series a plurality of sets of the plurality of the sequential execution for a plurality of the units.

Abstract: An information processing apparatus includes: an operating unit capable of recognizing a peripheral apparatus. The operating unit includes: a first recognizing unit configured to recognize, when a peripheral apparatus is connected to the operating unit and identification information about the connected peripheral apparatus is included in peripheral apparatus information including predetermined identification information, the connected peripheral apparatus as a first peripheral apparatus; and a second recognizing unit configured to recognize, when a peripheral apparatus is connected to the operating unit and the identification information about the connected peripheral apparatus is not included in the peripheral apparatus information, the connected peripheral apparatus as a second peripheral apparatus.

Abstract: An electronic device includes a battery, a detecting unit, a comparing unit, a control unit and a charging circuit. The detecting unit is electronically connected to a universal serial bus (USB) interface to detect and determine whether or not the connecting device is a power adapter. The comparing unit outputs a level signal depending upon the comparing unit comparing a input signal received by the USB interface with a voltage threshold. The control unit controls the battery either to be charged by the connecting device through the charging circuit or the battery to supply power to the connecting device through the USB interface according to the level signal.

Abstract: Systems and methods for deferring registration for Direct Memory Access (DMA) operations. An example method comprises: receiving a memory region registration request identifying a memory region for a direct memory access (DMA) operation; generating a local key for the memory region; deferring registration of the memory region until receiving a DMA work request referencing the local key; and responsive to receiving the DMA work request, registering the memory region for DMA transfer.

Abstract: Interrupt rate determination can include instructions to determine a quantity of instances of packet processing by an operating system during a first period of time, each instance corresponding to a particular interrupt request sent by a device, determine a quantity of bytes processed during the first period of time by the operating system, determine a speed of the device, determine a first interrupt rate to assign to the device for a second period of time based on the quantity of instances, the quantity of bytes processed, and the speed of the device during the first period of time, and set the interrupt rate to the device.

Abstract: A storage device includes a nonvolatile semiconductor memory module, a first interface circuit, and a second interface circuit conforming to an interface standard different from an interface standard of the first interface circuit. One of the first interface circuit and the second interface circuit is connected to the nonvolatile semiconductor memory module via first wiring, and to terminals of the storage device for connection to a host via second wiring. The other one of the first interface circuit and the second interface circuit is not connected to either the nonvolatile semiconductor memory module or the terminals.

Abstract: Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.

Abstract: A crate for shipping an information handling system includes a first side comprising an electro-magnetic protective material. The electro-magnetic protective material inhibits electro-magnetic intrusions into the information handling. The crate also includes a second side comprising a first portion comprising the electro-magnetic protective material, and a second portion devoid of the electro-magnetic protective material. The second portion passes a wireless electro-magnetic signal to the information handling system.

Abstract: The invention is directed a method for transferring at least one datum between a real-time task producing a datum and a real-time task consuming said datum. The method may include, in response to initiation of a transfer of a datum by a current instance of an initiating task: creating at least one DMA descriptor describing the DMA transfer expected for said datum; inserting DMA descriptors into a list of descriptors awaiting processing by a DMA controller, said DMA descriptors being inserted in a manner sorted based on a sorting criterion relating to a visibility date of the data and/or a temporal behavior of the tasks; processing the descriptors on the list of DMA descriptors by executing DMA requests; and executing the following instance of the initiating task based on termination of the processing a predefined set of DMA descriptors on the list of descriptors.

Abstract: A system can include a plurality of first server modules interconnected to one another via a communication network, each first server module including a first switch, at least one main processor, and at least one computation module coupled to the main processor by a bus, each computation module including a second switch, and a plurality of computation elements; wherein the second switches of the first server modules form a switching plane for the ingress and egress of network packets independent of any main processors of the first server modules.

Abstract: According to some embodiment, a backup storage system receives a plurality of input/output (IO) requests at the storage system. The IO requests include random IO requests and sequential IO requests. The storage system determines whether there is a pending random IO request from the plurality of IO requests. In response to determining that there is a pending random IO request, the storage system determines whether a total latency of the sequential IO requests exceeds a predicted latency of the pending random IO request. The storage system services the pending random IO request in response to determining that the total latency of the sequential IO requests exceeds the predicted latency of the pending random IO request.

Abstract: Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or made available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

Abstract: Examples of data polling using a chain sleep technique are disclosed. In one example, a computer-implemented method includes: computing a least common multiplier (LCM) based on a polling time for each of a plurality of devices deployed in a well operation to be polled; generating a sequence of polling elements, wherein each of the polling elements represents a multiple of the polling time for each of the plurality of devices, wherein the sequence of polling elements begins with the lowest polling time and ends with the LCM; sorting the sequence of polling elements from lowest value to highest value as an ordered list; calculating a distance between each of the polling elements of the ordered list; generating a polling chain based on the ordered list and the distance between each of the polling elements; and polling the plurality of devices in the well operation based on the polling chain.

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.

Abstract: A topology-aware parallel reduction method, system, and recording medium including a partitioning device configured to partition data in each accelerator of a plurality of accelerators into partitions based on a topology of connections between the plurality of accelerators and a control device configured to control, based on a topology of connections between the plurality of accelerators, a type of parallel reduction of data to use.

Abstract: A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system. Other embodiments are disclosed and claimed.

Abstract: A power supply system includes at least a first power supply module and at least one redundant power supply module. The at least one power supply module supplies power to an output terminal. The at least one redundant power supply module operates in a first state and in a second state. In the first state the second power supply module supplies power to the output terminal. In the second state the second power supply module provides standby power and operates in a burst mode (for example, such as a discontinuous conduction mode).

Abstract: A universal serial bus stack may use an emulation layer to grant a non-universal serial bus device access to universal serial bus drivers and applications. The universal serial bus stack may exchange a device communication at an emulation layer. The universal serial bus stack may translate between a universal serial bus communication and the device communication at the emulation layer, and then may exchange the universal serial bus communication at a universal serial bus client interface.