Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: Optimizing network driver performance and power consumption in multi-core processor-based systems is disclosed. In this regard, a multi-core processor-based system provides multiple processor cores comprising one or more power-optimized processor cores and one or more performance-optimized processor cores, and a network device configured to assign network streams to a plurality of interrupts. A network driver calculates a current throughput level of the network device, and determines whether a throughput mode of the network driver should be modified to a high-throughput mode. If so, the network driver assigns each interrupt to one of the performance-optimized processor cores, and disables system reassignment of interrupts among the processor cores.

Abstract: Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative embodiment, an MAUSB device may send USB configuration data to a host compute device. The host compute device may then perform a virtual enumeration of the USB devices based on the USB configuration data without necessarily communicating with the USB devices. The MAUSB device may perform an enumeration of the USB devices on behalf of the host compute devices without necessarily communicating with the host compute device. The USB devices may not be aware or have any indication that the USB device is not communicating with the host compute device during the enumeration process. Such an approach may improve the latency of USB enumeration over an MAUSB connection.

Abstract: A first medical device can receive a physiological parameter value from a second medical device. The second physiological parameter value may be formatted according to a protocol not used by the first medical device such that the first medical device is not able to process the second physiological parameter value to produce a displayable output value. The first medical device can pass the physiological parameter data from the first medical device to a separate translation module and receive translated parameter data from the translation module at the first medical device. The translated parameter data can be processed for display by the first medical device. The first medical device can output a value from the translated parameter data for display on the first medical device or an auxiliary device.

Abstract: A network adapter includes one or more ports for communicating over a communication network, a bus interface, and logic circuitry. The bus interface is configured to communicate over a bus. The logic circuitry is configured to receive bus configuration request packets from an originator, to control the bus interface to generate one or more bus configuration cycles in response to at least some of the bus configuration request packets, and, in response to the bus configuration cycles, to generate and send bus configuration response packets to the originator of the bus configuration request packets.

Abstract: Methods and apparatuses for protecting data integrity in a multiple path input/output environment are provided. When sending a write command that includes data to be written to a target device from an initiator device over a specified first path of a plurality of paths by which the target device is in communication with the initiator device when a fault in the first path is detected and the status of the write command indicates that the write command was fully transmitted to the target device, a second path of a plurality of paths is selected, a reset command is sent over the second path from the initiator device to the target device, and after sending the reset command, the data are retransmitted in a second write command that a path other than the first path from the initiator device to the target device.

Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.

Abstract: Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.

Abstract: Methods and devices for connecting an accessory device to a connector port of a mobile communication device and automatically detecting an operational mode of the connector port are provided. The method includes implementing a USB Type-C device detection at an electronic processor of the mobile communication device and monitoring a first and second pin of the connector port for pull-up and pull-down signals from a connected accessory. The method also includes interrupting the USB Type-C device detection when a pull-down signal is detected and determining whether an accessory signal is detected at a third pin of the connector port. The method also includes implementing a LMR accessory detection when the accessory signal is detected and completing the USB Type-C device detection when the accessory signal is not detected.

Abstract: Disclosed is a server system having a hot plug motherboard. The server system includes a motherboard module, at least one midplane board and at least one hard disk module. The motherboard module includes a plurality of motherboards. The midplane board is coupled by means of hot plugging to each of the motherboards. The midplane board includes at least one Peripheral Component Interconnect Express (PCIe) slot, and the PCIe slot is configured to be plugged with a PCIe card. The hard disk module includes a plurality of hard disks being coupled to the PCIe card through a signal wire.

Abstract: The disclosure relates to a function connection unit for connecting at least one parameterizable functional module, including at least one functional module connection configured to connect to the at least one parameterizable functional module; a communication interface that is configured to receive first parameter data records, the first parameter data records including parameter data for parameterizing the at least one parameterizable functional module and first parameter indices that index a memory area for the parameter data; and a processor configured to convert the first parameter indices into second parameter indices to obtain second parameter data records, the second parameter indices indexing a predetermined memory area of the at least one parameterizable functional module for storing the parameter data in the at least one parameterizable functional module.

Abstract: Described herein is a system for driver execution. A driver is loaded in a first domain with the driver controlling an associated device. In response to a request from the driver, the driver companion is loaded in a second domain different than the first domain, the second domain comprising a secure environment. The driver companion communicates with the associated device. Communications between the driver and the driver companion are managed (e.g., by an operating system framework). In response to a request from the driver, the driver companion is unloaded.

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a circuit structure that can be configured to operate in either the C-PHY mode or the D-PHY mode of the MIPI specification. In one device, the circuit structure can be included in a receiver of the device and configured to operate in the C-PHY mode. In another device, the circuit structure can be included in a receiver of the device and configured to operate in the D-PHY mode.

Abstract: A display device includes a first communication unit connected to one or more peripheral devices, a second communication unit that communicates with a remote controller, and a processor. If the processor is initialized in response to a power-on instruction through the second communication unit, the processor verifies whether a first peripheral device, which is selected as a source device that provides at least one source of video and audio signals, among the one or more peripheral devices is powered on within a first threshold time. If the first peripheral device is not powered on within the first threshold time, the processor transmits a power-on request for allowing the remote controller to power on the first peripheral device, to the remote controller through the second communication unit.

Abstract: A system includes a high speed bus and a plurality of multi-function modules coupled to the high speed bus. The plurality of multi-function modules includes at least one controller configured to execute control logic for the system. The plurality of multi-function modules also includes at least one arbitrator configured to manage the at least one controller. The plurality of multi-function modules further includes at least one input/output (IO) manager configured to interface between the at least one controller and at least one field device.

Abstract: Data and power are transmitted a master to a peripheral, with power communicated from a controller circuit board to the peripheral circuit board across data lines. Power is transmitted from the voltage regulator of the controller circuit board to an SPI or SSI master. Power over Synchronous Serial Interface (SSI) and Serial Peripheral Interface (SPI) uses Ethernet cable or custom 2 to 4-pair cable to move power high speed data between a microprocessor and a peripheral.

Abstract: To enable a fast configuration of a control or of a total plant, a control for the safe control of at least one machine is provided having at least one input unit for receiving input signals from at least one signal generator; having at least one output unit for outputting output signals to the at least one machine; having a control unit for generating the output signals in dependence on the input signals; and having a connection unit having at least one connection socket for connecting an external input device that can be used or configuring the control, wherein the connection unit has at least one connection terminal for connecting the signal generators and/or the machine and is separable from the control and wherein the connection socket can be removed from the connection unit or from the control and comprises a memory with configuration data of the control.

Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Abstract: Memory devices connected in a chain topology to a host controller that communicate using Low Voltage Differential Signaling (LVDS) and out-of-band signaling.

Abstract: Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.