Abstract: Interrupt rate determination can include instructions to determine a quantity of instances of packet processing by an operating system during a first period of time, each instance corresponding to a particular interrupt request sent by a device, determine a quantity of bytes processed during the first period of time by the operating system, determine a speed of the device, determine a first interrupt rate to assign to the device for a second period of time based on the quantity of instances, the quantity of bytes processed, and the speed of the device during the first period of time, and set the interrupt rate to the device.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A transmitter for establishing communication between a device and a differential network bus includes current driving means connected to each of the two conduction lines of the differential network bus, through a first and second conduction paths of the transmitter; at least one unidirectional current regulator for extracting a first current equal to a known ratio of a parasitic current circulating through the first conduction path, with a direction inverse to the driving current through the conduction path connected to one of the lines of the differential bus; means for obtaining, from the first current, a second current with a magnitude equal to the original magnitude of the parasitic current; and means for introducing the second current into the second conduction path connected to the other line of the differential bus.

Abstract: Electrical circuit control techniques in power systems are disclosed herein. In one embodiment, a supervisory computer in the power system can be configured to fit phasor measurement data from phasor measurement units into a Gaussian distribution with a corresponding Gaussian confidence level. When the Gaussian confidence level of the fitted Gaussian distribution is above a Gaussian confidence threshold, the supervisory computer can be configured to perform an ambient analysis on the received phasor measurement data to determine an operating characteristic of the power system. The supervisory computer can then automatically applying at least one electrical circuit control action to the power system in response to the determined operating characteristic.

Abstract: The disclosure provides an input and output recording device and method, CPU and data read and write operation method thereof. The input and output recording device is provided between a central processor CPU and a peripheral, and is configured to record data read and write operations between the CPU and the peripheral, wherein the data read and write operations comprise a data read and write operation initiated by the peripheral and a data read and write operation initiated by the CPU; the input and output recording device is further configured to request the CPU to process the data read and write operation initiated by the peripheral, and upon receiving an instruction sent by the CPU, send a data packet of the data read and write operation initiated by the peripheral to the CPU.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and a computer system are provided. The computer system includes an initialization component of a host. The initialization component obtains a process file for dynamically creating a processing component on a management platform on a BMC of the host, the process file defining a logic to be implemented by the processing component, the initialization component operating to load an operating system of the host. The initialization component sends the process file to the BMC. The initialization component further sends a message to the BMC, the message including data to be processed by the processing component.

Abstract: A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module. The host controller apparatus further includes a control module configured to transmit the plurality of instruction signals to the memory module via the command and address bus. The control module is configured to receive the loopback feedback signal from the memory module. The loopback feedback signal includes a looped-back composite version of the plurality of instruction signals. The control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

Abstract: Aspects of the disclosure provide for distributed flash interface module (FIM) processing in a solid state drive (SSD). Methods and apparatus lock a queue and retrieve a command from the queue. The command indicates an operation to be executed in conjunction with one or more non-volatile (NVM) dies of the SSD. The methods and apparatus then lock a NVM interface corresponding to the one or more NVM dies, determine whether the operation is a transfer operation, and execute the operation using the locked NVM interface according to whether the operation is the transfer operation. When the operation is determined to be the transfer operation, the queue is unlocked to allow execution of a second operation from the queue by a second controller in parallel with the operation executed by the controller. Thereafter, the NVM interface is unlocked after execution of the operation is complete.

Abstract: Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.

Abstract: A display apparatus for controlling a peripheral device and a method thereof are provided. The method may include transmitting, to a remote controller, a first turn-on signal to turn on the peripheral device; measuring a time interval between a first time when the display apparatus transmits the first turn-on signal to the remote controller and a second time when the display apparatus starts to receive content from the peripheral device in response to the first turn-on signal; and setting the measured time interval as a threshold time to determine whether the content is received from the peripheral device.

Abstract: A system and method for controlling the performance of one or more target devices. A connection request for a target device of a plurality of target devices is received at a serial attached SCSI (SAS) Expander from an SAS initiator device, wherein a maximum performance availability value is associated with the target device. If the current performance availability value of the target device indicates that the target device does have availability to service the connection request, the connection request from the SAS initiator device is accepted and a connection is established between the SAS initiator device and the target device. Alternatively, if the current performance availability value of the target device indicates that the target device does not have availability to service the connection request, the connection request from the SAS initiator device is rejected and a connection is not established between the SAS initiator device and the target device.

Abstract: An electronic apparatus includes a permutation circuit and an arbitration circuit. The permutation circuit is configured to apply to an input vector a permutation selected from a plurality of predefined permutations in response to a control word. The arbitration circuit is configured to receive a vector of requests for a resource, to instruct the permutation circuit to apply a randomly-selected permutation to the vector of requests, by configuring the permutation circuit with a corresponding randomly-selected control word so as to produce a permuted vector, to select an element of the permuted vector, to apply to the permuted vector an inverse of the randomly-selected permutation so as to produce an inversely-permuted vector, to identify an element of the inversely-permuted vector to which the selected element of the permuted vector is mapped, and to assign the resource to a client corresponding to the identified element of the inversely-permuted vector.

Abstract: A multi-direction connectable electronic module includes a circuit board, including a top surface, a bottom surface, and at least one side; and a plurality of connectors connected to the circuit board, each including a lateral magnetic connector, a shell, a longitudinal inter-locking part, and a lateral inter-locking part. The lateral inter-locking part is configured to connect with a first electronic building block along the lateral direction. The longitudinal inter-locking part is configured to stack with a second electronic building block along the longitudinal direction. The lateral magnetic connector is configured to magnetically connect with the first electronic building block. A plurality of through holes are formed on the shell. A lateral pin connector disposed on the at least one side of the circuit board includes a plurality of pins located at positions corresponding to the plurality of through holes, and is configured to electrically connect the first electronic building block.

Abstract: Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.

Abstract: According to at least some example embodiments of the inventive concepts, an electronic device includes an embedded storage device that is, configured to connect to a removable storage device, and configured to directly communicate with the removable storage device, when connected to the removable storage device; and an application processor connected to directly communicate with the embedded storage device and not directly connected with the removable storage device, wherein, the embedded storage device is configured to, in response to a disable command received from the application processor, decrease an amount of power supplied to all or some of circuits included in the embedded storage device, and provide a bypass path that is configured to transfer a normal command and data from the application processor to the removable storage device, when the removable storage device is connected to the bypass path.

Abstract: A topology-aware parallel reduction method, system, and recording medium including obtaining the GPU connection topology of each of the plurality of GPUs as a connection tree, transforming the connection tree into a three layer tree comprising an intra-root tree, an intra-node tree, and an inter-node tree, evenly partitioning each entry on each of the GPUS, and selectively transferring data either in either direction or in each direction, simultaneously, along the evenly partitioned three layer tree using a full-duplex configuration of a PCIe bandwidth.

Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: Optimizing network driver performance and power consumption in multi-core processor-based systems is disclosed. In this regard, a multi-core processor-based system provides multiple processor cores comprising one or more power-optimized processor cores and one or more performance-optimized processor cores, and a network device configured to assign network streams to a plurality of interrupts. A network driver calculates a current throughput level of the network device, and determines whether a throughput mode of the network driver should be modified to a high-throughput mode. If so, the network driver assigns each interrupt to one of the performance-optimized processor cores, and disables system reassignment of interrupts among the processor cores.

Abstract: Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative embodiment, an MAUSB device may send USB configuration data to a host compute device. The host compute device may then perform a virtual enumeration of the USB devices based on the USB configuration data without necessarily communicating with the USB devices. The MAUSB device may perform an enumeration of the USB devices on behalf of the host compute devices without necessarily communicating with the host compute device. The USB devices may not be aware or have any indication that the USB device is not communicating with the host compute device during the enumeration process. Such an approach may improve the latency of USB enumeration over an MAUSB connection.

Abstract: A first medical device can receive a physiological parameter value from a second medical device. The second physiological parameter value may be formatted according to a protocol not used by the first medical device such that the first medical device is not able to process the second physiological parameter value to produce a displayable output value. The first medical device can pass the physiological parameter data from the first medical device to a separate translation module and receive translated parameter data from the translation module at the first medical device. The translated parameter data can be processed for display by the first medical device. The first medical device can output a value from the translated parameter data for display on the first medical device or an auxiliary device.