Abstract: Communication systems and communication control methods are disclosed. In one example, a slave device belonging to a group of devices to which arbitration is applicable sequentially transmits a start bit and a first address including a first bit having a value different from a corresponding first bit of predetermined pattern data. A master device sequentially transmits the start bit and the predetermined pattern data. The master device arbitrates the master device and the first slave device based on the value of the first bit.

Abstract: Provided is a programmable controller capable of simplifying handshake processing between control devices. The programmable controller, which performs the handshake processing in conjunction with a reception-side device, is provided with an output signal area in which a signal to be output to the reception-side device is held, an input signal area in which a signal output by the reception-side device is held, a sequential program execution part configured to execute a sequential program, an output signal temporary area in which an output signal from the sequential program is held, and a handshake processing part configured to copy a signal state of the output signal temporary area in the output signal area and hold the signal state of the output signal area so that the input signal area is notified of a completion signal.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Systems and methods described herein facilitate configuration changes to an NIC teaming device while enabling multiple I/O threads continue to run through the NIC teaming device concurrently without interruption. At a given time, multiple configurations of the NIC teaming device, e.g., one for a current configuration of the NIC teaming device and one for a new configuration of the NIC teaming device, can co-exist. For the duration of one iteration, the current configuration of the NIC teaming device used by a specific I/O thread does not change and the new configuration of the NIC teaming device is not adopted by the I/O thread until the start of the next iteration. Once all of the I/O threads finish their current iteration, the configuration of the NIC teaming device is flipped from the current configuration to the new configuration and the current configuration is deleted.

Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: Ringing on the clock line on a synchronous serial data bus limits the maximum distance between the clock transmitter and receiver. The present disclosure provides a serial transmission protocol and a synchronous serial data bus for long distance serial data transmission between the clock source and the clock receiver that tolerates ringing on the transmission lines by constructing the clock signal at the receiver end of the link.

Abstract: An information handling system includes first and second compute nodes, each compute node including a central processing unit (CPU), a computational accelerator (CAC). An inter-accelerator transport (IAT) interface of each node connects to an IAT transport to provide an external interconnect, directly coupling first node GPUs with second node GPUs, for inter-node GPU-to-GPU (GtG) data traffic. Inter-node adapters on each node connect to an inter-node transport (INT) to provide an external interconnect coupling the GPUs of one node to the CPU/root of the other node for carrying inter-node non-GtG data traffic. Interconnects carrying non-GtG traffic, including the INT, may be ×16 PCIe 3.0 or later links while interconnects carrying GtG traffic, including the IAT interconnects, may be implemented as greater-than-PCIe (GTP) interconnects where GTP interconnects have a data transfer rate exceeding comparable PCIe data transfer rates, e.g., 16 GB/s per ×16 PCIE 3.0.

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Abstract: An intelligent function unit includes an input selector selecting, as an input signal, an actual input signal or a simulated input signal generated in advance; an output selector selecting whether to output an output signal to the second controlled device; and a calculator causing an input/output controller in which combination and order of use of general circuit blocks are set to process the input signal one step at a time and transmit the output signal to an engineering tool or causing the input/output controller in which combination and order of use of the general circuit blocks are set to process the input signal consecutively for a set period of two or more steps, store the output signal for each step in a logger, and transmit an output signal corresponding to the set period and stored in the logger to the engineering tool.

Abstract: A method includes processing a plurality of descriptors received from an electronic device. Each descriptor corresponds to a function of the electronic device. The processing includes determining a virtual function device corresponding to execution of at least one function based on a successful matching of one or more of the received descriptors with one or more driver files corresponding to at least one of the plurality of functions. The method also includes communicating an operating command to the virtual function device corresponding to execution of the at least one function based on an indication that the at least one function is to be executed. The operating command causes the virtual function device corresponding to execution of the at least one function to be operated on the electronic device. Two or more functions of the plurality of functions associated with different resources of the electronic device are selectable for execution.

Abstract: An example processor-implemented method for accessing peripheral devices with the present disclosure includes establishing connection between a portable computing device and a dock, determining a pairing status between the portable computing device and the dock, and managing access to at least one peripheral device by the portable computing device based on the pairing status. The dock is associated with the at least one peripheral device.

Abstract: A system having a data bus, bus controller(s), remote terminal(s) and a logger. The data bus has an inverted differential line and a non-inverted differential line. The bus controller(s) are electrically coupled to the data bus. The remote terminal(s) are electrically coupled to the data bus. The logger has a bus transceiver and a controller. The bus transceiver is electrically coupled to the data bus. The controller is electrically coupled to the transceiver. The controller is configured to: capture a non-inverted data stream from the bus transceiver, capture an inverted data stream from the bus transceiver, convert the non-inverted data stream into non-inverted packets having a packet size, convert the inverted data stream into inverted packets having the packet size; and write the non-inverted data packets and inverted data packets to a non-volatile memory.

Abstract: Described herein are features related to a bus based timed input output module (TIO) for use in control systems of physical systems, particularly where the physical systems are safety critical systems. When the TIO is powered on, one or more operations are performed by the TIO, wherein the one or more operations, when performed by the TIO: 1) cause the TIO to be non-functional, thereby preventing the TIO from improperly or accidentally activating a Component in communication with the TIO; 2) clears the TIO of previous operations (if any); and 3) facilitates compatibility of the TIO with an arbitrary Component.

Abstract: A display apparatus for controlling a peripheral device and a method thereof are provided. The method may include transmitting, to a remote controller, a first turn-on signal to turn on the peripheral device; measuring a time interval between a first time when the display apparatus transmits the first turn-on signal to the remote controller and a second time when the display apparatus starts to receive content from the peripheral device in response to the first turn-on signal; and setting the measured time interval as a threshold time to determine whether the content is received from the peripheral device.

Abstract: A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.

Abstract: A field device commissioning system includes a commissioning tool, a communication module and an IO module. The commissioning tool is configured to communicate with a client in a plurality of communications. The commissioning tool is configured to perform a parallel execution of executing a plurality of loop processing logics that includes at least one input loop check or at least one output loop check in parallel for all of a plurality of channels which belongs to each slot in each unit, in accordance with the plurality of request for executions of loop checks from the client in the plurality of communications. The commissioning tool is configured to perform in series a plurality of the sequential executions for a plurality of the slots in each unit, wherein each execution including the plurality of loop processing logics. The commissioning tool may be configured to perform in series a plurality of sets of the plurality of the sequential execution for a plurality of the units.

Abstract: An information processing apparatus includes: an operating unit capable of recognizing a peripheral apparatus. The operating unit includes: a first recognizing unit configured to recognize, when a peripheral apparatus is connected to the operating unit and identification information about the connected peripheral apparatus is included in peripheral apparatus information including predetermined identification information, the connected peripheral apparatus as a first peripheral apparatus; and a second recognizing unit configured to recognize, when a peripheral apparatus is connected to the operating unit and the identification information about the connected peripheral apparatus is not included in the peripheral apparatus information, the connected peripheral apparatus as a second peripheral apparatus.

Abstract: An electronic device includes a battery, a detecting unit, a comparing unit, a control unit and a charging circuit. The detecting unit is electronically connected to a universal serial bus (USB) interface to detect and determine whether or not the connecting device is a power adapter. The comparing unit outputs a level signal depending upon the comparing unit comparing a input signal received by the USB interface with a voltage threshold. The control unit controls the battery either to be charged by the connecting device through the charging circuit or the battery to supply power to the connecting device through the USB interface according to the level signal.