Patents Examined by Brian Young
  • Patent number: 10225555
    Abstract: A method and apparatus of entropy coding for a video encoder or decoder using multiple-table based Context-Based Adaptive Binary Arithmetic Coder (CABAC) are disclosed. In one embodiment, a current bin of a binary data of a current coding symbol is encoded or decoded according to a probability of a binary value of the current bin and the probability of the binary value is updated according to the binary value of the current bin for a next bin by using multiple-parameter probability models. Each multiple-parameter probability model is updated using at least one lookup table with the individual set of probability state as a table index to access contents of said at least one lookup table. In another embodiment, the range update is calculated for a range interval based on middle value of the range interval.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: March 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 10211535
    Abstract: Low-profile broadband patch antennas capable of radiating circularly polarized (CP) signals utilizing a single probe in accordance with embodiments of the invention are disclosed. In many embodiments, the patch antenna includes a ground plane, a patch plate, at least one dielectric or foam substrate, and a feed probe. In several embodiments, the patch plate includes a first plate and a second plate that can be connected via first and second connecting bars. In various embodiments, the connection of the first and second plates can expose first and second slots as further discussed below. In a variety of embodiments, the feed probe can be a coaxial cable having an inner and outer conductor where the inner conductor connects to the first plate and the outer conductor connects to the ground plane.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 19, 2019
    Assignee: The Regents of the University of California
    Inventors: Yahya Rahmat-Samii, Harish Rajagopalan, Joshua M. Kovitz, Jean Paul Santos
  • Patent number: 10211844
    Abstract: The disclosure relates converting an analog input signal to a digital output signal in a number of successive approximation cycles. A sampled analog input signal is received, and a decision node is loaded from a decision tree stored in memory, where each decision node in the decision tree stores an optimal threshold value and an address to one or more next decision nodes. The optimal threshold value, a first output flag and a second output flag associated with a currently loaded decision node is read from the decision tree in the memory, and the sampled first analog input signal is compared with the optimal threshold value and, based on a result of the comparison, a next decision node is loaded from the decision tree stored in memory according to the address associated with the currently loaded decision node or the digital output signal is output.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 19, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Arkady Molev-Shteiman, Xiao-Feng Qi
  • Patent number: 10205248
    Abstract: Antenna structures and methods of operating the same are described. An antenna structure may include an antenna carrier, a first antenna disposed on the first antenna carrier and coupled to a first radio frequency (RF) feed, a second antenna disposed on the first antenna carrier and coupled to a second RF feed, a third antenna disposed on the first antenna carrier and coupled to a third RF feed, and a fourth antenna disposed on the first antenna carrier and coupled to a fourth RF feed. The first antenna and the second antenna may be located along a first axis of the antenna carrier that passes through a center of the antenna carrier. The third antenna and the fourth antenna may be located along a second axis of the antenna carrier that passes through a center of the antenna carrier.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 12, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Ming Zheng, Adrian Napoles, Jay Praful Desai
  • Patent number: 10200055
    Abstract: Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 5, 2019
    Assignee: Analog Devices Global
    Inventors: Peter Enright, Martina Mincica, Fergus Downey
  • Patent number: 10200054
    Abstract: In a general aspect, an apparatus can include a signal analyzer configured to analyze a signal associated with a processing pipeline, and a dynamic element matching (DEM) selection module configured to select a DEM algorithm from a plurality of DEM algorithms based on the analysis performed by the signal analyzer. The apparatus can include a set of circuit elements where each circuit element from the set of circuit elements has the same logical configuration, and a circuit element selection module configured to select a subset of the set of circuit elements based on the selected DEM algorithm.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 5, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hrvoje Jasa, Tyler Daigle, Andrew Jordan, Gregory Maher
  • Patent number: 10193565
    Abstract: The present disclosure relates to a compressive encoding apparatus, a compressive encoding method, a decoding apparatus, a decoding method, and a program which can provide a lossless compression technology having a higher compression rate. An encoding unit of the compressive encoding apparatus converts M bits of a ??-modulated digital signal into N bits (M>N) with reference to a first conversion table, and when the M bits are not able to be converted into the N bits with the first conversion table, converts the M bits into the N bits with reference to a second conversion table. When the number of bit patterns of the N bits is P, the first conversion table is a table storing (P?1) number of codes having higher generation frequencies for past bit patterns, and the second conversion table is a table storing (P?1) number of codes having higher generation frequencies for past bit patterns, which follow those of the first conversion table.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 29, 2019
    Assignee: Sony Corporation
    Inventor: Takao Fukui
  • Patent number: 10181857
    Abstract: An analog-to-digital converter includes an integrator, a single comparator, a successive approximation result register, and correction circuitry. The comparator is coupled to an output of the integrator. The successive approximation result register is coupled to an output of the comparator. The correction circuitry is configured to determine whether a sum of a reference voltage and an output voltage of the integrator changes an output of the comparator. The correction circuitry is also configured to, responsive to the sum of the reference voltage and the output of the integrator not changing the output of the comparator, add twice the reference voltage to the output of the integrator to produce a bit value at the output of the comparator, and select a bit value to be loaded into the successive approximation result register based on the bit value at the output of the comparator.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dimitar T. Trifonov
  • Patent number: 10177777
    Abstract: A dual-sensor signal collecting circuit comprises circuit (11), a second sensor signal collecting circuits, an AD sampling circuit, an AND gate determination circuit and a collected signal averaging circuit. Output ends of the sensor signal collecting circuits are connected to respective input ends of the AND gate determination circuit, respective input ends of the collected signal averaging circuit and a first AD sampling port of the AD sampling circuit; an output end of the AND gate determination circuit is connected to a power supply end of the collected signal averaging circuit; an output end of the collected signal averaging circuit is connected to the first AD sampling port of the AD sampling circuit. When the sensors operate normally, the collected signal averaging circuit outputs an average sampling value to the first AD sampling port, when one is damaged, a sampling value of the one operating normally is output to the first AD sampling port.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 8, 2019
    Assignee: Qingdao GoerTek Technology Co., Ltd.
    Inventors: Kun Dong, Jiajin Zhan, Chenbin Fu, Litang Chen, Xiaojian Liu
  • Patent number: 10177775
    Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jagannathan Venkataraman, Eeshan Miglani
  • Patent number: 10177782
    Abstract: Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Sudhir K. Satpathy, James D. Guilford, Sanu K. Mathew, Vinodh Gopal, Vikram B. Suresh
  • Patent number: 10171102
    Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 1, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Hajime Shibata, Yunzhi Dong, Zhao Li, Trevor Clifford Caldwell, Wenhua William Yang
  • Patent number: 10164652
    Abstract: A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 25, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Kobayashi, Takayasu Narukawa, Masaya Tsuneoka, Masayuki Funakoshi, Norihiro Yamaguchi, Takahiro Okanoue
  • Patent number: 10158179
    Abstract: A phased antenna array comprises a plurality of antennas and photodiodes arranged on a substrate. Each antenna is driven by an electrical signal output by the photodiode. The photodiodes each receive an optical signal via an optical fiber. The optical fibers conform to the sheet-like shape of the antenna array (which may be planar or curved) and optically communicate with a corresponding photodiode via a corresponding reflector, such as a ninety degree reflector. The reflectors may comprise a v-groove in a silicon substrate on which the optical fiber is positioned and a reflecting surface. Each reflector may be attached to the substrate or a ground plane positioned parallel to the substrate and the optical fiber may connect to the reflector in a direction running parallel to the phased antenna array. This optical feed network may accommodate tight spacing of the antenna elements (such as spacing less than 5 mm apart) with a thin profile.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 18, 2018
    Assignee: Phase Sensitive Innovations, Inc.
    Inventors: Janusz Murakowski, Dennis Prather, Peng Yao
  • Patent number: 10153542
    Abstract: The mobile satellite system is a vehicle that is adapted for use in satellite communications. The mobile satellite system is a trailer that is towed by a motorized vehicle. The mobile satellite system comprises a dish, a dish mount, a chassis, a suspension, a plurality of tracks, and a control system. The suspension attaches the plurality of tracks to the chassis. The dish mount attaches the dish to the chassis. The control system is mounted in the chassis. The dish is an antenna that is used to establish a communication link with a targeted satellite. The control system is an electronic device. The control system: 1) manages the targeting and positioning of the dish; and, 2) receives messages and other communications from a targeted satellite; and, optionally, 3) transmits messages and other communications to the targeted satellite.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 11, 2018
    Inventor: Paul Catrow
  • Patent number: 10153558
    Abstract: A component including a substrate with dielectric coating on the substrate. The electrical reactance of the dielectric coating configured for the propagation of electromagnetic surface waves. The dielectric coating is arranged as a plurality of discrete pathways. Also a signal transmission system including a component, an electromagnetic surface wave transmitter coupled to the substrate, and an electromagnetic surface wave receiver also coupled to the substrate.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 11, 2018
    Assignee: ROLLS-ROYCE PLC
    Inventors: Daniel Clark, Werner P. Schiffers
  • Patent number: 10148280
    Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Avnera Corporation
    Inventors: Wai Lee, Jianping Wen, Garry N. Link
  • Patent number: 10128867
    Abstract: A hierarchical unary/thermometer coder comprises a cascade of lower level coders that minimize clock loading and clock transitions by only enabling the clocking of a circuit when that circuit is required to change state, thereby minimizing power consumption. At the lowest level, a stage-1 circuit produces a two-bit unary/thermometer code using two NAND gates, an inverter, and a single set-reset latch. An output of the latch forms a least significant bit (LSB) and is used to control transitions of the next most significant bit. A stage-2 circuit produces a four-bit unary/thermometer code using two stage-1 circuits and a NOR gate. A stage-3 circuit produces an eight-bit unary/thermometer code using two stage-2 circuits and a NAND gate. The circuit associated with each higher order bit is only enabled when the next lower bit has been set. Outputs are also provided for generating a “running one” or “running zero” code.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 13, 2018
    Assignee: SEMICONDUCTOR IDEAS TO THE MARKET EINDHOVEN
    Inventor: Michiel Johannes Karel van Elzakker
  • Patent number: 10120609
    Abstract: A compute device to generate deterministic compressed streams receives a current string to be matched to one or more prior instances of the current string, the current string being located within an input buffer and the one or more prior instances located within a history buffer. The compute device identifies a limited subset of index memory designated for storing pointers to the prior instances, identifying a reserved slop region in the index memory, and compares the current string to a prior instance, locating the at least one prior instance using at least one pointer to the at least one prior instance. The at least one pointer is stored within the limited subset of the index memory, and the compute device also prohibits use of any pointers stored in the reserved slop region of the index memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel F. Cutter
  • Patent number: 10116275
    Abstract: A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 30, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Noriyuki Murashima