Abstract: Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state.

Abstract: In an example embodiment, an apparatus includes: a first sampling capacitor to switchably couple between an input analog voltage, a reference voltage (VREF) and a ground voltage; a second sampling capacitor to switchably couple between the reference voltage and the ground voltage; and a comparator having a first input terminal to couple to the first sampling capacitor and a second input terminal to couple to the second sampling capacitor. The comparator may be configured to compare a voltage level at the second input terminal to a sum voltage based at least in part on the input analog voltage to generate at least one bit of a digital output.

Abstract: A precision bipolar digital-to-analog converter (DAC) that provides a bipolar current output having a substantially fixed zero center point is provided. The DAC includes digital-to-analog converter circuitry configured to provide, responsive to a reference signal indicative of the digital data, a first analog current signal having a first potential and a second analog current signal having a second potential, subtractor circuitry configured to provide a bipolar current signal by subtracting the second analog current signal from the first analog current signal, the bipolar current signal having a zero center point, and first control circuitry electrically coupled to the subtractor circuitry and to the digital-to-analog converter circuitry, and configured to modify the second potential so that the second potential equals the first potential.

Abstract: A reflector device having first and second reflector plates to which a reflective surface is attached, respectively, at a prescribed angle of inclination in relation to an axis of rotation, wherein the first reflector plate (1) and the second reflector plate are positioned so as to face one another, and the first reflector plate and/or the second reflector plate are/is capable of rotating around the axis of rotation.

Abstract: An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.

Abstract: Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

Abstract: A method for generating Huffman codewords to encode a dataset includes selecting a Huffman tree type from a plurality of different Huffman tree types. Each of the Huffman tree types specifies a different range of codeword length in a Huffman tree. A Huffman tree of the selected type is produced by: determining a number of nodes available to be allocated as leaves in each level of the Huffman tree accounting for allocation of leaves in each level of the Huffman tree; allocating nodes to be leaves such that the number of nodes allocated in a given level of the Huffman tree is constrained to be no more than the number of nodes available to be allocated in the given level; and assigning the leaves to symbols of the dataset based an assignment strategy selected from a plurality of assignment strategies to produce symbol codeword information.

Abstract: A wall-mountable wireless control device may comprise a yoke, a faceplate assembly, an antenna, a radio-frequency communication circuit, and/or a control circuit. The radio-frequency communication circuit may be configured to transmit or receive radio-frequency signals via the antenna. The faceplate assembly may comprise a conductive element that is configured to operate as a radiating element of the antenna when the faceplate assembly is attached to the yoke. The conductive element may comprise a conductive material on the front surface of the faceplate. The conductive element may be attached to a rear surface of the faceplate (e.g., as a conductive backer). The conductive element may be located inside of the faceplate. The conductive element may comprise metallization applied to a plastic carrier of the faceplate. The faceplate assembly may comprise an adapter plate comprising a surface on which the conductive element is located.

Abstract: A module for wireless communication includes: a module body which (i) is plate-shaped, has (ii) a structure having a plurality of layers, and (iii) has a circuit region; and a folded dipole which is situated circumferentially around the circuit region and has a first dipole half situated in a first level of the module body, and a second dipole half situated in a second level of the module body. The first dipole half and the second dipole half are separated by a layer of the module body, and are connected to one another in electrically conductive fashion through a first via and a second via extending through the layer.

Abstract: A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.

Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.

Abstract: A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal.

Abstract: An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.

Abstract: A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Abstract: A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

Abstract: Approaches for staged data compression are provided, where each stage reflects a progressive increase in granularity, resulting in a scalable approach that exhibits improved efficiency and compression performance. The first stage comprises a long-range block-level compressor that determines redundancies on a block-level basis (based on entire data blocks, as opposed to partial segments within data blocks). The second stage comprises a long-range byte-level compressor that compresses an uncompressed block based on byte segments within the block that match previously transmitted segments. The duplicate segments are replaced with pointers to matching segments within a decompressor cache. Nonmatching segments of the data block are left uncompressed and passed to a third stage short-range compressor (e.g., a grammar-based compressor). The staged progression in granularity provides advantages of maximizing the compression gain while minimizing processing and storage requirements of the compressor and decompressor.

Abstract: A data compression device including a processor to perform a procedure comprising: obtaining data of a predetermined number (Z) of digits in a time series; and performing a compression process on the data. The data is obtained by encoding a vibration state of a measurement target. The compression process includes: deleting upper digits when the upper digits do not include significant information; and adding a unique code to a top of the upper digits when the upper digits include significant information. A digit number (X) of the upper digits is smaller than the predetermined number (Z).

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.