Patents Examined by Brook Kebede
  • Patent number: 10729006
    Abstract: [Objective] To provide a wiring substrate for electronic component inspection apparatus which includes a first laminate of resin layers with a plurality of pads for probe provided on its front surface and a second laminate of ceramic layers disposed on the back side of the first laminate and which, despite joining by brazing of a plurality of studs to the back surface of the second laminate, is free from deformation of resin of the first laminate caused by softening or the like and from accidental formation of a short circuit between brazing material layers used for the brazing and external connection terminals formed on the back surface of the second laminate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 28, 2020
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takakuni Nasu, Yousuke Kondo, Kouta Kimata, Guangzhu Jin
  • Patent number: 10727387
    Abstract: Alight emitting device includes a substrate including a base member including a front surface, a rear surface opposite to the front surface, a bottom surface perpendicular to the front surface, and a top surface opposite to the bottom surface, a first wiring portion located on the front surface, and a second wiring portion located on the rear surface; a light emitting element electrically connected with the first wiring portion; and a first reflective member covering a lateral surface of the light emitting element and the front surface of the base member. The base member has a recessed portion opened on the rear surface and the bottom surface. The substrate includes a third wiring portion covering an inner wall of the recessed portion and electrically connected with the second wiring portion, and a via in contact with the first wiring portion, the second wiring portion and the third wiring portion.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 28, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Gensui Tamura
  • Patent number: 10727219
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 10721845
    Abstract: Disclosed is a system and method for optimizing cooling efficiency of a data center is disclosed. The system may comprise an importing module, a Computational fluid dynamics (CFD) modeling module, a scope determination module, a metrics computation module, an identification module and a recommendation module. The importing module may be configured to import data associated to the data center. The CFD modeling module may be configured to leverage an external CFD Analysis tool in order to develop a CFD model of the data center. The scope determination module may be configured to determine a scope for optimizing the cooling efficiency of the data center. The metrics computation module may be configured to compute metrics based upon the data. The identification module may be configured to identify inefficiency and a cause producing the inefficiency. The recommendation module may be configured to facilitate optimizing cooling efficiency of the data center.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 21, 2020
    Assignee: Tata Consultancy Services Limited
    Inventors: Harshad Girish Bhagwat, Umesh Singh, Sankara Narayanan D, Arun Varghese, Amarendra Kumar Singh, Rajesh Jayaprakash, Anand Sivasubramaniam
  • Patent number: 10714335
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 14, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Patent number: 10714340
    Abstract: According to an embodiment, a wafer W includes a layer EL to be etched, an organic film OL, an antireflection film AL, and a mask MK1, and a method MT according to an embodiment includes a step of performing an etching process on the antireflection film AL by using the mask MK1 with plasma generated in a processing container 12, in the processing container 12 of a plasma processing apparatus 10 in which the wafer W is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film SX on the surface of the mask MK1, and steps ST6a to ST7 of etching the antireflection film AL by removing the antireflection film AL for each atomic layer by using the mask MK1 on which the protective film SX is formed.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 14, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Tomoyuki Oishi
  • Patent number: 10714417
    Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack
  • Patent number: 10707807
    Abstract: Solar panel assemblies and wall sections using such assemblies are described. In one solar panel assembly, there is a mounting post and three or more triangular shaped panels. Each triangular shaped panel is a solar panel responsive to a first spectrum of light and transparent to a second spectrum of light. The solar panel assembly also includes hinges which connect the triangular shaped panels to the mounting post. The at least three triangular shaped panels can move between a flat configuration and an inverted pyramid configuration. In a further embodiment of the solar panel assembly, the triangular shaped panels form a first solar panel layer, and the assembly also includes one or more additional solar panel layers. Each of the additional solar panel layers being responsive to an associated spectrum of light.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 7, 2020
    Inventor: Jonathan Jacques
  • Patent number: 10707213
    Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
  • Patent number: 10707139
    Abstract: An etching method for an IC is provided. The etching method includes retrieving processing data including a pattern-density and at least one etching parameter of an etching process for a semiconductor device; determining end point time by consulting a table which records historical information of a plurality of PDs, the etching parameter and the EP time; compensating for the PD and the EP time by adjusting the etching parameter to perform the etching process; and performing the etching process on another semiconductor device based on the adjusted etching parameter, the PD and the EP time to manufacture the IC.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Sheng Lien, Shih-Ta Yu
  • Patent number: 10699950
    Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Terry A. Spooner
  • Patent number: 10700202
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10700240
    Abstract: The present disclosure provides a light-emitting device. The light-emitting device includes a light emitting area and an electrode area. The light-emitting area includes a first semiconductor structure having a first active layer and a second semiconductor structure having a second active layer. The electrode area includes an external electrode structure surrounding the second semiconductor structure in a top view. The light-emitting area has a shape of circle or polygon in the top view. When the first semiconductor structure is driven by a first current, the first active layer can emit a first light with a first main wavelength. When the second semiconductor structure is driven by a second current, the active layer of the second semiconductor structure can emit a second light with a second main wavelength.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: June 30, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Yao-Ru Chang, Wen-Luh Liao, Chun-Yu Lin, Hsin-Chan Chung, Hung-Ta Cheng
  • Patent number: 10692965
    Abstract: Methods of forming an inductor using dry processes are described. A cavity is laser drilled in an insulator. A first magnetic material layer is printed in the cavity. An Ag conductive ink is printed on the first magnetic material layer and a second magnetic material layer printed on the ink. The ink has a trace sandwiched between the first and second magnetic material layers that provides a majority of the inductance of the inductor. A protective insulating layer protects the second magnetic material layer from a wet chemistry solution when contacts are formed to the ink. The second magnetic material layer and ink are deposited in or on the cavity.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Chong Zhang, Andrew J. Brown, Sheng Li, Sai Vadlamani, Ying Wang
  • Patent number: 10693040
    Abstract: A light emitting device includes a semiconductor layer, and a light emitting layer disposed in the semiconductor layer and having a composition ratio of Ga(1-x)InxN. x is greater than 0.14 but less than 0.16 to emit a green light from the light emitting layer, or greater than 0.22 but less than 0.26 to emit a blue light from the light emitting layer.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Bae Kim, Sang Kyun Im, Hyun Kyung Kim, Young Hun Choi
  • Patent number: 10685275
    Abstract: Embodiments of the invention relate to processes for fabricating a smart device, e.g. smart card, and configurations for smart card devices with greater reliability and lifespan, and improved finish. In the smart card device comprising of laminated substrate layers interposing a flexible film having conductor pattern thereon, at least one flip chip for operating the smart card device is embedded in a first substrate such that the first substrate provides an encapsulation to the at least one flip chip, wherein the at least one flip chip is arranged at a position in a first vertical plane; and a contact pad, for providing electrical connection when the smart card device is inserted into a smart card reader, is arranged at a position in a second vertical plane, wherein the first vertical plane is non-overlapping with the second vertical plane.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 16, 2020
    Inventors: Eng Seng Ng, Sze Yong Pang
  • Patent number: 10677046
    Abstract: Various examples are provided for gas leakage detection from geologic storage sites. In one example, a system for detection of gas leakage from a geologic storage site includes permanent down-hole gauges (PDGs) disposed at different depths within a well and an evaluation system that can determine a three-dimensional (3D) location of the gas leakage from the geologic storage site and a leakage indicator. The 3D location and leakage indicator can be determined using pressure data provided by the PDGs. The geologic storage site can store, e.g., CO2, natural gas or other type of gas. In another example, a method for detecting gas leakage from a geologic storage site includes receiving pressure data provided by PDGs disposed within one or more wells associated with the geologic storage site, determining key performance indicators using the pressure data and determining a 3D location and a leakage indicator using the key performance indicators.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 9, 2020
    Assignee: West Virginia University
    Inventors: Shahab D. Mohaghegh, Seyed Alireza Haghighat
  • Patent number: 10679915
    Abstract: A package structure includes a plurality of first dies, a first encapsulant, and a first redistribution structure. The first encapsulant encapsulates the first dies. The first redistribution structure is disposed on the first dies and the first encapsulant. The first redistribution structure includes a dielectric layer covering a top surface and sidewalls of the first encapsulant.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yin Hsieh, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 10680070
    Abstract: A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Hao Li, Lei Wang, Longjie Zhao, Xiaoxiang Sun
  • Patent number: 10672705
    Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yongan Xu, Junli Wang, Yann Mignot, Joe Lee