Abstract: A semiconductor memory device with improved performance and reliability is provided. The semiconductor memory device includes a substrate having a cell region and a peripheral region, a cell region isolation layer that separates the cell region from the peripheral region, and a plurality of cell gate structures, each including a cell gate electrode that extends in a first direction. The cell region includes a plurality of active areas that extend in a second direction different from the first direction, and are between a respective cell element isolation layer and the cell region isolation layer. Each of the active areas includes a first portion and a second portion separated by the cell gate structure, the second portion of the active area is on both sides of a respective one of the first portion of the active area. The active areas includes a normal active area and a dummy active area.

Abstract: A manufacturing method of a semiconductor device includes: a first step of forming a laminated film by growing crystals on a sapphire substrate, forming an insulating film on a laminated film, and forming contact holes at an electrical connection point of an n-GaN layer and an electrical connection point of a p-GaN layer in the insulating film to produce a first member; a second step of forming a conductive layer on the first member to produce a second member in which the conductive layer electrically connects the electrical connection point of the n-GaN layer and the electrical connection point of the p-GaN layer; a third step of irradiating the second member with excitation light and measuring light emission generated in the second member; and a fourth step of forming a first pad electrode and a second pad electrode to produce a semiconductor device.

Abstract: A display panel includes a display substrate and a touch function layer. The display substrate includes a substrate, a first barrier wall, an organic structure and a film encapsulation layer. The organic structure is on the substrate and surrounds the first barrier wall. The organic structure includes at least one organic layer. The film encapsulation layer is on a side of the first barrier wall away from the substrate. An inorganic encapsulation layer in the film encapsulation layer covers the first barrier wall. On the substrate, an orthographic projection of the inorganic encapsulation layer is non-overlapping with an orthographic projection of the organic structure. The touch function layer includes an inorganic dielectric layer contacting the film encapsulation layer. The inorganic dielectric layer covers the first barrier wall. On the substrate, an orthographic projection of the inorganic dielectric layer is non-overlapping with the orthographic projection of the organic structure.

Abstract: Molybdenum (Mo) metal-on-metal (MoM) deposition methods for providing true bottom-up fill in vias and/or other gap features in device structures. These device structures contain metal at the bottom surface and have dielectric sidewalls. The deposition process provides molybdenum growth only, in some cases, on the metal film/layer to provide a selective process that can be called a metal-on-metal (MoM) process. The Mo MoM deposition process described herein are not limited to thin films (e.g., films less than 50 ?) and can be used to deposit thicker films (e.g., greater than 50 ? in some cases and greater than 200 ? in other useful cases) on metal surfaces while no, or substantially no, deposition is found on dielectric surfaces.

Abstract: A display substrate, manufacturing method thereof, and display device. In the display substrate, a gate insulating pattern is located at a side of an active layer, a metal conductive layer is at least partially located at a side of the gate insulating pattern. The gate insulating pattern includes a first opening, the active layer includes a second opening, an orthographic projection of the second opening on the base substrate is located within an orthographic projection of the first opening on the base substrate, the metal conductive layer includes a main body part and an extension part, the extension part is electrically connected with the active layer exposed by the first opening, and the conductive structure is overlapped with the extension part, and includes a connection part extending to the second opening and electrically connecting the active layer on two sides of the second opening.

Abstract: A semiconductor device includes peripheral active patterns on a substrate, first and second peripheral trench regions adjacent the peripheral active patterns, a first isolation liner on inner surfaces of the first and second peripheral trench regions, a second isolation liner on the first isolation liner in the first and second peripheral trench regions, and a device isolation layer on the second isolation liner in the first and second peripheral trench regions. The device isolation layer includes a seam therein in the second peripheral trench region. A width of the first peripheral trench region is greater than a width of the second peripheral trench region at a first height corresponding to top surfaces of the peripheral active patterns with respect to the substrate.

Abstract: A method of depositing titanium nitride is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing titanium nitride which utilizes a direct microwave plasma. In some embodiments, the direct microwave plasma has a high plasma density and low ion energy. In some embodiments, the plasma is generated directly above the substrate surface.

Abstract: A method for manufacturing a semiconductor device includes stacking an etch target layer and an etching mask layer on a substrate having first through third regions, forming first photoresist patterns on the etching mask layer in the first and second regions and a second photoresist pattern to completely cover the third mask layer in the third region, etching the etching mask layer using the first and second photoresist patterns as etching masks to form first mask patterns on the first and second regions and a second mask pattern on the third region, forming a filling pattern in a first opening between first mask patterns on the second region, etching the etch target layer using the first and second mask patterns and the filling pattern as etching masks to form first patterns including second openings on the first region and a bulk pattern covering second and third regions of the substrate.

Abstract: A semiconductor device includes a substrate including a cell region and a core/peripheral region, a bit line structure disposed on the substrate of the cell region and including a polysilicon structure, a barrier pattern, a metal pattern and a capping pattern that are stacked on each other, and a gate structure on the substrate of the core/peripheral region, the gate structure including a gate insulation pattern, a polysilicon pattern, a carbon-containing pattern, a barrier structure, a metal pattern and a capping pattern that are stacked on each other.

Abstract: A method for producing a solar cell, including the following steps: a) providing a substrate having a front side and a back side in a deposition apparatus, and b) coating the substrate in situ with two layers, including b1) oxidizing, by exposing the substrate to an oxygen-containing gas and a first plasma, to create an oxide layer and b2) subsequently depositing a silicon layer or SiC layer by exposure to a gas containing silicon, an optional gas containing carbon and a second plasma, wherein step b) is carried out under vacuum in the deposition apparatus and the vacuum is maintained continuously during step b).

Abstract: Each pixel of a display apparatus includes a first transistor, a second transistor connected to a first gate of the first transistor and a data line, a third transistor connected to the first gate of the first transistor and a first voltage line, a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor, and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are disposed on a same layer.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

Abstract: An integrated circuit device including a first cell block on a substrate that includes a first cell area, a first dummy cell area surrounding the first cell area in a plan view, the first dummy cell area including first active regions and second active regions in an outer periphery of the first dummy cell area, the first active regions each having a first size and the second active regions each having a second size larger than the first size, first and second word lines extending in a first direction and alternating with each other in a second direction, each of the first word lines including a first landing area extending between a second active region and a first active region, the first active region being near and apart from the second active region in the second direction, and first word line contacts on the first landing area may be provided.

Abstract: Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.

Abstract: A quantum dot material includes: quantum dot bodies and a ligand material coordinated to the quantum dot bodies; the quantum dot material further includes: a cross-linking agent, the cross-linking agent includes at least two photoresponsive group and a linking group bonding the at least two photoresponsive groups. Under light illumination, each photoresponsive group in the at least two photoresponsive groups is bonded to the ligand material by a carbon-hydrogen insertion reaction to form a cross-linked ligand material; a solubility of the cross-linked ligand material in a solvent is less than a solubility of the ligand material and the cross-linking agent in the solvent.

Abstract: A display device has a panel having a display, a plurality of light sources and light guiding bodies provided side by side below the rear surface of the panel, and a case having holding spaces provided side by side below the rear surface of the panel, one light source and one light guiding body being placed in each of the plurality of holding spaces. The plurality of light sources selectively emit light so as to selectively display a plurality of indicator patterns at the display. A cover film is integrally formed on the surface of the panel. The upper surface of the case, facing the rear surface of the panel, has a plurality of exposing portions from which the upper ends of the plurality of light guiding bodies are exposed. Each exposing portion has the shape of the indicator pattern in a plan view.

Abstract: A method for particle abatement in a semiconductor apparatus is provided. In a preferred embodiment, the method comprises processing a substrate in a process chamber of the semiconductor processing apparatus. The processing comprises loading the substrate in the process chamber having one or more inner surfaces, providing a reaction gas mixture to the process chamber, thereby forming a substrate film and a chamber wall film, and loading the substrate out of the process chamber. The method further comprises repeating the processing step one or more times until the chamber wall film has reached a pre-determined chamber wall film thickness, upon which exposing the inner surfaces to an ambient, thereby modifying at least an upper portion of the chamber wall film, thus reducing a probability of particle formation in the process chamber.

Abstract: A vertical memory device includes a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers contact the memory channel structure, respectively. The gate electrode structure contacts a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which extends through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.

Abstract: Semiconductor devices and methods of forming the same include a top transistor that includes a first channel and a first gate. A bottom transistor includes a second channel and a second gate that has a top surface at a same height as a top surface of the first gate. A gate barrier includes a horizontal part between the bottom transistor and the top transistor and a vertical part that extends from the horizontal part to a same height as the top surfaces of the first gate and the second gate.

Abstract: A diode radiation sensor having charge multiplication diodes and comprising a substrate with a front and a rear surface; a first layer of a semiconductor material doped with a first type of doping and arranged on the front surface of the substrate; a second layer of a semiconductor material doped with a second type of doping of electrically opposite sign to the first type and arranged to create a high electric field region between the first and the second layer; a third layer of a semiconductor material doped with a the second type of doping; a first isolation region interposed between a lateral edge of a charge multiplication diode and the first and the second layer of the semiconductor materials and extending into the substrate from the front surface to the third layer so as to create a working area electrically separated from the first and the second layer.