Abstract: A method of depositing titanium nitride is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing titanium nitride which utilizes a direct microwave plasma. In some embodiments, the direct microwave plasma has a high plasma density and low ion energy. In some embodiments, the plasma is generated directly above the substrate surface.

Abstract: A method for manufacturing a semiconductor device includes stacking an etch target layer and an etching mask layer on a substrate having first through third regions, forming first photoresist patterns on the etching mask layer in the first and second regions and a second photoresist pattern to completely cover the third mask layer in the third region, etching the etching mask layer using the first and second photoresist patterns as etching masks to form first mask patterns on the first and second regions and a second mask pattern on the third region, forming a filling pattern in a first opening between first mask patterns on the second region, etching the etch target layer using the first and second mask patterns and the filling pattern as etching masks to form first patterns including second openings on the first region and a bulk pattern covering second and third regions of the substrate.

Abstract: A semiconductor device includes a substrate including a cell region and a core/peripheral region, a bit line structure disposed on the substrate of the cell region and including a polysilicon structure, a barrier pattern, a metal pattern and a capping pattern that are stacked on each other, and a gate structure on the substrate of the core/peripheral region, the gate structure including a gate insulation pattern, a polysilicon pattern, a carbon-containing pattern, a barrier structure, a metal pattern and a capping pattern that are stacked on each other.

Abstract: A method for producing a solar cell, including the following steps: a) providing a substrate having a front side and a back side in a deposition apparatus, and b) coating the substrate in situ with two layers, including b1) oxidizing, by exposing the substrate to an oxygen-containing gas and a first plasma, to create an oxide layer and b2) subsequently depositing a silicon layer or SiC layer by exposure to a gas containing silicon, an optional gas containing carbon and a second plasma, wherein step b) is carried out under vacuum in the deposition apparatus and the vacuum is maintained continuously during step b).

Abstract: Each pixel of a display apparatus includes a first transistor, a second transistor connected to a first gate of the first transistor and a data line, a third transistor connected to the first gate of the first transistor and a first voltage line, a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor, and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are disposed on a same layer.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

Abstract: An integrated circuit device including a first cell block on a substrate that includes a first cell area, a first dummy cell area surrounding the first cell area in a plan view, the first dummy cell area including first active regions and second active regions in an outer periphery of the first dummy cell area, the first active regions each having a first size and the second active regions each having a second size larger than the first size, first and second word lines extending in a first direction and alternating with each other in a second direction, each of the first word lines including a first landing area extending between a second active region and a first active region, the first active region being near and apart from the second active region in the second direction, and first word line contacts on the first landing area may be provided.

Abstract: Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.

Abstract: A quantum dot material includes: quantum dot bodies and a ligand material coordinated to the quantum dot bodies; the quantum dot material further includes: a cross-linking agent, the cross-linking agent includes at least two photoresponsive group and a linking group bonding the at least two photoresponsive groups. Under light illumination, each photoresponsive group in the at least two photoresponsive groups is bonded to the ligand material by a carbon-hydrogen insertion reaction to form a cross-linked ligand material; a solubility of the cross-linked ligand material in a solvent is less than a solubility of the ligand material and the cross-linking agent in the solvent.

Abstract: A display device has a panel having a display, a plurality of light sources and light guiding bodies provided side by side below the rear surface of the panel, and a case having holding spaces provided side by side below the rear surface of the panel, one light source and one light guiding body being placed in each of the plurality of holding spaces. The plurality of light sources selectively emit light so as to selectively display a plurality of indicator patterns at the display. A cover film is integrally formed on the surface of the panel. The upper surface of the case, facing the rear surface of the panel, has a plurality of exposing portions from which the upper ends of the plurality of light guiding bodies are exposed. Each exposing portion has the shape of the indicator pattern in a plan view.

Abstract: A method for particle abatement in a semiconductor apparatus is provided. In a preferred embodiment, the method comprises processing a substrate in a process chamber of the semiconductor processing apparatus. The processing comprises loading the substrate in the process chamber having one or more inner surfaces, providing a reaction gas mixture to the process chamber, thereby forming a substrate film and a chamber wall film, and loading the substrate out of the process chamber. The method further comprises repeating the processing step one or more times until the chamber wall film has reached a pre-determined chamber wall film thickness, upon which exposing the inner surfaces to an ambient, thereby modifying at least an upper portion of the chamber wall film, thus reducing a probability of particle formation in the process chamber.

Abstract: A vertical memory device includes a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers contact the memory channel structure, respectively. The gate electrode structure contacts a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which extends through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.

Abstract: Semiconductor devices and methods of forming the same include a top transistor that includes a first channel and a first gate. A bottom transistor includes a second channel and a second gate that has a top surface at a same height as a top surface of the first gate. A gate barrier includes a horizontal part between the bottom transistor and the top transistor and a vertical part that extends from the horizontal part to a same height as the top surfaces of the first gate and the second gate.

Abstract: A diode radiation sensor having charge multiplication diodes and comprising a substrate with a front and a rear surface; a first layer of a semiconductor material doped with a first type of doping and arranged on the front surface of the substrate; a second layer of a semiconductor material doped with a second type of doping of electrically opposite sign to the first type and arranged to create a high electric field region between the first and the second layer; a third layer of a semiconductor material doped with a the second type of doping; a first isolation region interposed between a lateral edge of a charge multiplication diode and the first and the second layer of the semiconductor materials and extending into the substrate from the front surface to the third layer so as to create a working area electrically separated from the first and the second layer.

Abstract: The formation of a tungsten film is promoted when forming the tungsten film using tungsten chloride on an upper layer side of a titanium silicon nitride film. A titanium silicon nitride film is formed on one surface side of a semiconductor wafer as a substrate, and an intermediate film for promoting the formation of the tungsten film made of the tungsten chloride is formed on the upper layer side of the titanium silicon nitride film by using a gas for forming the intermediate film. The tungsten film is formed on an upper layer side of the intermediate film by using a gas of the tungsten chloride.

Abstract: A method for producing a layer of solid material includes: providing a solid body having opposing first and second surfaces, the second surface being part of the layer of solid material; generating defects by means of multiphoton excitation caused by at least one laser beam penetrating into the solid body via the second surface and acting in an inner structure of the solid body to generate a detachment plane, the detachment plane including regions with different concentrations of defects; providing a polymer layer on the solid body; and generating mechanical stress in the solid body such that a crack propagates in the solid body along the detachment plane and the layer of solid material separates from the solid body along the crack.

Abstract: A strip substrate comprises a dielectric layer comprising a unit region and a saw line region, a saw line pattern on the saw line region, a conductive dummy pattern extending from the saw line pattern and toward the unit region, and power/ground patterns on the unit region. The power/ground pattern includes a first lateral surface that extends in a first direction and is proximate to the saw line pattern, a second lateral surface that extends in a second direction and is proximate to the conductive dummy pattern, and a third lateral surface that connects the first lateral surface and the second lateral surface.

Abstract: Assemblies, systems, and methods are described herein for a removable lid for flip chip-ball grid array (FC-BGA) packages. An example removable lid assembly for an integrated circuit (IC) package includes at least one pedestal configured to be attached to a substrate, a lid configured to be reversibly secured to the at least one pedestal, and a plurality of fasteners configured to reversibly secure the lid to the at least one pedestal. In an installed state of the removable lid assembly in which the removable lid assembly is attached to the substrate, the lid is spaced from the substrate and the electrical components of the substrate. In the installed state, the removable lid assembly enhances a stiffness of the substrate, thereby reducing warpage of the substrate during a reflow process applied to the substrate. Corresponding systems and methods are also provided.

Abstract: A method includes forming a first electrode, and depositing a dielectric layer over the first electrode. The dielectric layer has a first dielectric constant and a first thickness. A dielectric capping layer is deposited over the dielectric layer. The dielectric capping layer has a second dielectric constant higher than the first dielectric constant, and a second thickness smaller than the first thickness. The method further includes forming a second electrode over the dielectric capping layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.

Abstract: A display device includes a base substrate and first to third color filter layers. The base substrate includes pixel regions and a light blocking region. A pixel region from among the pixel regions includes first to third light emitting regions emitting light of different colors from each other. The light blocking region surrounds the first to third light emitting regions. The first color filter layer is on the base substrate, has a first color, and overlaps the first light emitting regions and an entirety of the light blocking region. The second color filter layer is on the base substrate, has a second color, and overlaps the second light emitting regions and a portion of the light blocking region. The third color filter layer is on the base substrate, has a third color, and overlaps the third light emitting regions and an entirety of the light blocking region.