Patents Examined by Brook Kebede
  • Patent number: 11075324
    Abstract: A method of producing an outcoupling element for an optoelectronic component includes A) providing quantum dots each having a core made of a semiconductor material, B) applying an inorganic or a phosphonate-containing ligand shell on a respective core of the quantum dots, and C) introducing the quantum dots with the ligand shell into a matrix material, wherein introducibility of the quantum dots with the ligand shell is facilitated compared to the quantum dots produced in step A), and the outcoupling element is transparent for radiation from the red and/or IR region.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 27, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Georg Dirscherl, Marcus Adam, Guido Kickelbick
  • Patent number: 11075121
    Abstract: A method for fabricating a semiconductor device includes forming an initial fin structure on a semiconductor substrate; and forming a plurality of first dummy gate structures and a second dummy gate structure across the initial fin structure. The second dummy gate structure is formed between two adjacent first dummy gate structures, and includes a second dummy-gate-structure body. The method also includes forming a trench in the initial fin structure by etching and removing the second dummy-gate-structure body and a portion of the initial fin structure under the second dummy-gate-structure body. The trench divides the initial fin structure to form two fin structures. The method further includes forming a trench isolation layer in the trench and an interlayer dielectric layer on the plurality of first dummy gate structures. The interlayer dielectric layer covers a portion of the semiconductor substrate and the two fin structures adjacent to the trench.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Huanyun Zhang, Jian Wu
  • Patent number: 11069848
    Abstract: A method for forming a unique, environmentally-friendly micron scale autonomous electrical power source is provided in a configuration that generates renewable energy for use in electronic systems, electronic devices and electronic system components. The configuration includes a first conductor with a facing surface conditioned to have a low work function, a second conductor with a facing surface having a comparatively higher work function, and a dielectric layer, not more than 200 nm thick, sandwiched between the respective facing surfaces of the first conductor and the second conductor. The autonomous electrical power source formed according to the disclosed method is configured to harvest minimal thermal energy from any source in an environment above absolute zero.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: July 20, 2021
    Assignee: Face International Corporation
    Inventor: Clark D Boyd
  • Patent number: 11069561
    Abstract: An electronic device comprises a dielectric structure, interconnect structures extending into the dielectric structure and having uppermost vertical boundaries above uppermost vertical boundaries of the dielectric structure, an additional barrier material covering surfaces of the interconnect structures above the uppermost vertical boundaries of the dielectric structure, an isolation material overlying the additional barrier material, and at least one air gap laterally intervening between at least two of the interconnect structures laterally-neighboring one another. Each of the interconnect structures comprises a conductive material, and a barrier material intervening between the conductive material and the dielectric structure. The at least one air gap vertically extends from a lower portion of the isolation material, through the additional barrier material, and into the dielectric structure. Electronic systems and method of forming an electronic device are also described.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toyonori Eto, Kuo-Chen Wang
  • Patent number: 11038008
    Abstract: Provided is a display apparatus capable of reducing generation of defects during manufacturing of the display apparatus or while in use after being manufactured. The display apparatus includes a substrate including a bending area between a first area and a second area, the substrate being bent in the bending area about a bending axis; an inorganic insulating layer over the substrate and including a first feature that is either a first opening or a first groove, the first feature positioned to correspond to the bending area; and an organic material layer at least partially filling the first feature, and including a second feature that is a second opening or a second groove, the second feature extending along an edge of the substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 15, 2021
    Inventors: Yoonsun Choi, Hyunchul Kim
  • Patent number: 11037919
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 15, 2021
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 11037903
    Abstract: A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 15, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Darrell Truhitte
  • Patent number: 11031489
    Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Patent number: 11018144
    Abstract: An anti-fuse cell includes a control device and an anti-fuse element is introduced. The control device includes a source node, a drain node and a gate node, wherein the gate node is electrically coupled to a word line and the drain node is electrically coupled to a bit line. The anti-fuse element includes a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer of the anti-fuse element physically stacks upon and directly contacts a metal layer that is electrically connected to the source node of the control device, and first conductive layer is electrically coupled to a program line through a via. An anti-fuse cell having multiple anti-fuse elements and a chip having a plurality of anti-fuse cells are also introduced.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11018191
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and include replacement gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 25, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 11018294
    Abstract: A method for regulating a phase transformation of a hydrogen-containing transition metal oxide comprises steps of: providing a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein the hydrogen-containing transition metal oxide is in form of a first phase, A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; soaking the hydrogen-containing transition metal oxide with a first ionic liquid capable of providing hydrogen ions and oxygen ions; and applying a gating voltage to the hydrogen-containing transition metal oxide with the first ionic liquid as a gate to regulate the phase transformation of the hydrogen-containing transition metal oxide.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 25, 2021
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
  • Patent number: 11011495
    Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 18, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
  • Patent number: 11004719
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; and performing a bonding of a fourth level above the third level, where the fourth level includes a second single crystal layer, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having a same doping type.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 11, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11004788
    Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Seul-Ki Hong, Hyun-Soo Kim, Sang-Hyun Lee
  • Patent number: 10998472
    Abstract: A light emitting device includes: a light emitting element having an emission face and lateral faces; a wavelength conversion member having a first face and a second face which opposes the first face, the wavelength conversion member being disposed on the emission face of the light emitting element so that the first face faces the emission face; a reflecting member disposed on lateral face sides of the light emitting element and covering at least a portion of outer lateral faces of the wavelength conversion member, and a cover member disposed on an upper face of the reflecting member while being adjacent to peripheral ends of the wavelength conversion member. The cover member contains at least one of a reflecting substance and a coloring substance. A body color of the wavelength conversion member and a body color of the cover member are the same color or similar colors.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 4, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Hirosuke Hayashi
  • Patent number: 10998200
    Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Mei-Yee Shek, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 10991721
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Raghuveer S. Makala, Masaaki Higashitani
  • Patent number: 10984988
    Abstract: Provided are a method of manufacturing a ring-shaped member and the ring-shaped member. A method of manufacturing a ring-shaped member to be placed in a process chamber of a substrate processing apparatus includes arranging one silicon member and another silicon member to cause one abutting surface of the one silicon member and another abutting surface of the other silicon member to abut on each other, heating the one abutting surface and the other abutting surface through optical heating to melt silicon on a surface of the one abutting surface and silicon on a surface of the other abutting surface such that silicon melt is caused to flow into a gap between the one abutting surface and the other abutting surface, and cooling the one abutting surface and the other abutting surface to crystallize the silicon melt forming a silicon adhesion part.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 20, 2021
    Assignee: THINKON NEW TECHNOLOGY JAPAN CORPORATION
    Inventors: Atsushi Ikari, Satoshi Fujii
  • Patent number: 10982324
    Abstract: Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 20, 2021
    Assignee: Siltronic AG
    Inventor: Joerg Haberecht
  • Patent number: 10978348
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 13, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed