Abstract: The formation of a tungsten film is promoted when forming the tungsten film using tungsten chloride on an upper layer side of a titanium silicon nitride film. A titanium silicon nitride film is formed on one surface side of a semiconductor wafer as a substrate, and an intermediate film for promoting the formation of the tungsten film made of the tungsten chloride is formed on the upper layer side of the titanium silicon nitride film by using a gas for forming the intermediate film. The tungsten film is formed on an upper layer side of the intermediate film by using a gas of the tungsten chloride.

Abstract: A method for producing a layer of solid material includes: providing a solid body having opposing first and second surfaces, the second surface being part of the layer of solid material; generating defects by means of multiphoton excitation caused by at least one laser beam penetrating into the solid body via the second surface and acting in an inner structure of the solid body to generate a detachment plane, the detachment plane including regions with different concentrations of defects; providing a polymer layer on the solid body; and generating mechanical stress in the solid body such that a crack propagates in the solid body along the detachment plane and the layer of solid material separates from the solid body along the crack.

Abstract: A strip substrate comprises a dielectric layer comprising a unit region and a saw line region, a saw line pattern on the saw line region, a conductive dummy pattern extending from the saw line pattern and toward the unit region, and power/ground patterns on the unit region. The power/ground pattern includes a first lateral surface that extends in a first direction and is proximate to the saw line pattern, a second lateral surface that extends in a second direction and is proximate to the conductive dummy pattern, and a third lateral surface that connects the first lateral surface and the second lateral surface.

Abstract: Assemblies, systems, and methods are described herein for a removable lid for flip chip-ball grid array (FC-BGA) packages. An example removable lid assembly for an integrated circuit (IC) package includes at least one pedestal configured to be attached to a substrate, a lid configured to be reversibly secured to the at least one pedestal, and a plurality of fasteners configured to reversibly secure the lid to the at least one pedestal. In an installed state of the removable lid assembly in which the removable lid assembly is attached to the substrate, the lid is spaced from the substrate and the electrical components of the substrate. In the installed state, the removable lid assembly enhances a stiffness of the substrate, thereby reducing warpage of the substrate during a reflow process applied to the substrate. Corresponding systems and methods are also provided.

Abstract: A method includes forming a first electrode, and depositing a dielectric layer over the first electrode. The dielectric layer has a first dielectric constant and a first thickness. A dielectric capping layer is deposited over the dielectric layer. The dielectric capping layer has a second dielectric constant higher than the first dielectric constant, and a second thickness smaller than the first thickness. The method further includes forming a second electrode over the dielectric capping layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.

Abstract: A method producing a microelectromechanical component. A dielectric layer is structured on an upper side of a substrate forming a grating, and a blind hole is formed beneath the grating. A cover layer is arranged on the dielectric layer closing the blind hole. A layer sequence is arranged on the cover layer and above the blind hole. Functional structures are formed in the layer sequence and an access channel extending through the layer sequence to the blind hole is formed. A further substrate is connected to the substrate. The functional structures are enclosed in a cavity, connected to the blind hole, between the substrate and the further substrate. Another blind hole is formed on an underside of the substrate. The blind hole is opened in the region of the other blind hole. A cavity internal pressure is set, and the blind hole is closed.

Abstract: A display device includes a base substrate and first to third color filter layers. The base substrate includes pixel regions and a light blocking region. A pixel region from among the pixel regions includes first to third light emitting regions emitting light of different colors from each other. The light blocking region surrounds the first to third light emitting regions. The first color filter layer is on the base substrate, has a first color, and overlaps the first light emitting regions and an entirety of the light blocking region. The second color filter layer is on the base substrate, has a second color, and overlaps the second light emitting regions and a portion of the light blocking region. The third color filter layer is on the base substrate, has a third color, and overlaps the third light emitting regions and an entirety of the light blocking region.

Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal; surface-activating the first hybrid interface layer and the second hybrid interface layer by particle bombardment; and bringing the surface-activated first hybrid interface layer and the surface-activated second hybrid interface layer into contact, such that the first and second insulators bond together and the first and second metals bond together at the same time.

Abstract: A display device includes a substrate including a first surface and a second surface opposite to the first surface, a display on the first surface, a first wiring pad located on the second surface and electrically connected to the display, an external connection terminal on the second surface, connection wiring located on the second surface and electrically connecting the first wiring pad and the external connection terminal, and a dummy conductor being a protrusion on the second surface. The protrusion overlaps none of the first wiring pad, the external connection terminal, and the connection wiring in a plan view.

Abstract: A laser annealing method performed on a reflective photomask may include preparing a reflective photomask including a pattern area and a border area surrounding the pattern area and irradiating a laser beam onto the border area of the reflective photomask. The irradiating of the laser beam may include split-irradiating a plurality of laser beam spots onto the border area. Each of the plurality of laser beam spots may be shaped using a beam shaper. The beam shaper may include a blind area, a transparent area at a center of the blind area, and a semitransparent area between the blind area and the transparent area. Each of the plurality of laser beam spots may include a center portion passing through the transparent area and having a uniform energy profile and an edge portion passing through the semitransparent area and having an inclined energy profile.

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.

Abstract: Provided is a manufacturing method of a semiconductor device, comprising: performing a zincate treatment on a first metal layer provided above a semiconductor substrate with a zincate solution; forming a nickel-plated layer above the first metal layer; and forming a gold-plated layer above the nickel-plated layer, wherein in the performing the zincate treatment, a flow rate of the zincate solution supplied to a bath for performing the zincate treatment is 16 L/min or more and 20 L/min or less.

Abstract: A memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: An actuator according to one aspect of the present invention includes a first member in which a shape is transformed from a first position, which is either rolled or flat, to a second position different from the first position, and a restoring force is stored when the shape is transformed from the first position to the second position, and a second member which is joined to the first member along the length direction of the first member and in which the shape of the second position is stored.

Abstract: Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

Abstract: Various embodiments of methods are provided to control formation of self-assembled monolayers (SAMs) used in an area-selective deposition (ASD) process, and thus, prevent defects in the ASD process. In the disclosed embodiments, a SAM structure is formed via a spin-on process that includes: (a) a spin coating step for coating a surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, the semiconductor substrate having a target material and a non-target material exposed on the substrate surface, and (b) an anneal step for heat treating the semiconductor substrate to chemically bond the SAM-forming molecules to the non-target material exposed on the substrate surface. By controlling and/or varying process parameter(s) utilized during the anneal step, the embodiments disclosed herein improve the selectivity of the SAM structure to the non-target material and prevent defects from occurring when a film is subsequently deposited onto the target material.

Abstract: A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. Each of the lower electrodes includes a first electrode layer having a cylindrical shape, a first insertion layer disposed on the first electrode layer and having a cylindrical shape, a second electrode layer disposed on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer. At least one of the first electrode layer and the second electrode layer has a first stress, and the first insertion layer has a second stress, different from the first stress. The first stress is one of tensile stress and compressive stress, and the second stress is the other of the tensile stress and the compressive stress.