Abstract: A method producing a microelectromechanical component. A dielectric layer is structured on an upper side of a substrate forming a grating, and a blind hole is formed beneath the grating. A cover layer is arranged on the dielectric layer closing the blind hole. A layer sequence is arranged on the cover layer and above the blind hole. Functional structures are formed in the layer sequence and an access channel extending through the layer sequence to the blind hole is formed. A further substrate is connected to the substrate. The functional structures are enclosed in a cavity, connected to the blind hole, between the substrate and the further substrate. Another blind hole is formed on an underside of the substrate. The blind hole is opened in the region of the other blind hole. A cavity internal pressure is set, and the blind hole is closed.

Abstract: A display device includes a base substrate and first to third color filter layers. The base substrate includes pixel regions and a light blocking region. A pixel region from among the pixel regions includes first to third light emitting regions emitting light of different colors from each other. The light blocking region surrounds the first to third light emitting regions. The first color filter layer is on the base substrate, has a first color, and overlaps the first light emitting regions and an entirety of the light blocking region. The second color filter layer is on the base substrate, has a second color, and overlaps the second light emitting regions and a portion of the light blocking region. The third color filter layer is on the base substrate, has a third color, and overlaps the third light emitting regions and an entirety of the light blocking region.

Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal; surface-activating the first hybrid interface layer and the second hybrid interface layer by particle bombardment; and bringing the surface-activated first hybrid interface layer and the surface-activated second hybrid interface layer into contact, such that the first and second insulators bond together and the first and second metals bond together at the same time.

Abstract: A display device includes a substrate including a first surface and a second surface opposite to the first surface, a display on the first surface, a first wiring pad located on the second surface and electrically connected to the display, an external connection terminal on the second surface, connection wiring located on the second surface and electrically connecting the first wiring pad and the external connection terminal, and a dummy conductor being a protrusion on the second surface. The protrusion overlaps none of the first wiring pad, the external connection terminal, and the connection wiring in a plan view.

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.

Abstract: A laser annealing method performed on a reflective photomask may include preparing a reflective photomask including a pattern area and a border area surrounding the pattern area and irradiating a laser beam onto the border area of the reflective photomask. The irradiating of the laser beam may include split-irradiating a plurality of laser beam spots onto the border area. Each of the plurality of laser beam spots may be shaped using a beam shaper. The beam shaper may include a blind area, a transparent area at a center of the blind area, and a semitransparent area between the blind area and the transparent area. Each of the plurality of laser beam spots may include a center portion passing through the transparent area and having a uniform energy profile and an edge portion passing through the semitransparent area and having an inclined energy profile.

Abstract: Provided is a manufacturing method of a semiconductor device, comprising: performing a zincate treatment on a first metal layer provided above a semiconductor substrate with a zincate solution; forming a nickel-plated layer above the first metal layer; and forming a gold-plated layer above the nickel-plated layer, wherein in the performing the zincate treatment, a flow rate of the zincate solution supplied to a bath for performing the zincate treatment is 16 L/min or more and 20 L/min or less.

Abstract: A memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: An actuator according to one aspect of the present invention includes a first member in which a shape is transformed from a first position, which is either rolled or flat, to a second position different from the first position, and a restoring force is stored when the shape is transformed from the first position to the second position, and a second member which is joined to the first member along the length direction of the first member and in which the shape of the second position is stored.

Abstract: Various embodiments of methods are provided to control formation of self-assembled monolayers (SAMs) used in an area-selective deposition (ASD) process, and thus, prevent defects in the ASD process. In the disclosed embodiments, a SAM structure is formed via a spin-on process that includes: (a) a spin coating step for coating a surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, the semiconductor substrate having a target material and a non-target material exposed on the substrate surface, and (b) an anneal step for heat treating the semiconductor substrate to chemically bond the SAM-forming molecules to the non-target material exposed on the substrate surface. By controlling and/or varying process parameter(s) utilized during the anneal step, the embodiments disclosed herein improve the selectivity of the SAM structure to the non-target material and prevent defects from occurring when a film is subsequently deposited onto the target material.

Abstract: Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

Abstract: A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. Each of the lower electrodes includes a first electrode layer having a cylindrical shape, a first insertion layer disposed on the first electrode layer and having a cylindrical shape, a second electrode layer disposed on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer. At least one of the first electrode layer and the second electrode layer has a first stress, and the first insertion layer has a second stress, different from the first stress. The first stress is one of tensile stress and compressive stress, and the second stress is the other of the tensile stress and the compressive stress.

Abstract: The present disclosure provides a quantum dot ligand, a quantum dot-ligand system and a quantum dot material, belonging to the field of display technology. The quantum dot ligand includes an X group, a Y group and a Z group. The Y group is configured to provide at least two binding sites, among which at least one binding site is configured to bind with the X group, and the remaining binding site is configured to bind with the Z group. The X group is a coordination group configured to form a coordination bond with a surface of a quantum dot. The Z group is a saturated 3- to 5-membered heterocyclic group containing O or S.

Abstract: A surface treatment composition of the present invention is a surface treatment composition that are supplied as a vapor to a surface of a wafer having an uneven pattern on the surface and used to form a water-repellent protective film on the surface, the surface treatment composition containing a silylating agent and a solvent, in which the silylating agent contains a trialkylsilylamine, the solvent contains at least one or more selected from the group consisting of glycol ether acetate and glycol acetate, and a total content of the glycol ether acetate and the glycol acetate is 50% by mass or more in 100% by mass of a total amount of the solvent.

Abstract: A semiconductor device includes a substrate having a first conductivity type and an epitaxial layer disposed on the substrate. A first trench and a second trench are disposed in the epitaxial layer. A first body region and a second body region both having a second conductivity type are disposed in the epitaxial layer, and located on two sides of the first trench, respectively. A first source region and a second source region both having the first conductivity type are disposed on the first body region and the second body region, respectively. A first electrode is disposed in the first trench. A source contact structure includes a first portion disposed in the first trench and is electrically connected to the first source region and the second source region. A first gate is disposed in the second trench.

Abstract: The present disclosure provides a method for cleaning a vacuum system used in the manufacture of OLED devices. The method includes performing pre-cleaning for cleaning at least a portion of the vacuum system, and performing plasma cleaning using a remote plasma source.

Abstract: A semiconductor device includes a first conductive line, a second conductive line, a third conductive line, a first semiconductor layer, a memory layer and a conductive layer. The first conductive line and the second conductive line extend along a first direction. The third conductive line extends along a second direction substantially perpendicular to the first direction. The first semiconductor layer extends along the second direction to surround the third conductive line. The memory layer is disposed between the first semiconductor layer and the second conductive line. The conductive layer is disposed between the memory layer and the first semiconductor layer.