Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first interconnect structure disposed in a semiconductor substrate, first and second dielectric layers disposed over the semiconductor substrate, a second interconnect structure disposed in the first and second dielectric layers, and a third interconnect structure disposed in the semiconductor substrate. The first interconnect structure includes a first conductive line and a first manganese-containing layer. The second interconnect structure includes a second conductive line and a second manganese-containing layer. The third interconnect structure includes a third conductive line and a third manganese-containing layer. The third manganese-containing layer of the third interconnect structure and the first manganese-containing layer of the first interconnect structure are made of a same material.

Abstract: An image sensor, including a shared pixel including two sub pixels of a 1×2 structure and sharing a floating diffusion region on each of the two sub pixels through a metal wiring, unit pixels surrounding the floating diffusion region, within the shared pixel, separated from each other by front-side deep trench isolation, and each including a photodiode, a transfer transistor adjacent to the floating diffusion region and on each of the unit pixels, a reset transistor and a selection transistor on a first unit pixel located in a first quadrant among the unit pixels, a conversion gain transistor on a second unit pixel located in a second quadrant among the unit pixels, and a source follower transistor on a third unit pixel located in a third quadrant and a fourth unit pixel located in a fourth quadrant among the unit pixels.

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. The semiconductor substrate includes a circuit pattern region and a peripheral region surrounding the circuit pattern region, an activation layer on the second surface of the semiconductor substrate and having a plurality of circuit patterns in the circuit pattern region, and at least one scattering detection pattern in the peripheral region and having a plurality of circuit cells that generate leakage current based on a scattered beam or heat of a laser.

Abstract: To manufacture a redistribution layer for an integrated circuit, a first insulating layer is formed on a conductive interconnection layer of a wafer. A conductive body is then formed in electrical contact with the interconnection layer. The conductive body is then covered with an insulating region having an aperture that exposes a surface of the conductive body. The surface of the conductive body and the insulating region are then covered with an insulating protection layer having a thickness less than 100 nm. This insulating protection layer is configured to provide a protection against oxidation and/or corrosion of the conductive body.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first interconnect structure disposed in a semiconductor substrate, first and second dielectric layers disposed over the semiconductor substrate, a second interconnect structure disposed in the first and second dielectric layers, and a third interconnect structure disposed in the semiconductor substrate. The first interconnect structure includes a first conductive line and a first manganese-containing layer. The second interconnect structure includes a second conductive line and a second manganese-containing layer. The third interconnect structure includes a third conductive line and a third manganese-containing layer. The third manganese-containing layer of the third interconnect structure and the first manganese-containing layer of the first interconnect structure are made of a same material.

Abstract: A method of manufacturing an integrated circuit device includes forming multiple conductive layers on an upper surface of a substrate, forming a capping structure arranged on the multiple conductive layers and extending in a first direction, forming a plurality of bit lines extending in the first direction by patterning the multiple conductive layers using the capping structure, and forming a plurality of buried layers in a space between neighboring bit lines of the plurality of bit lines. The capping structure includes a lower insulating capping layer, an insulating layer disposed on the lower insulating capping layer, and a polysilicon layer disposed on the insulating layer. The polysilicon layer includes a material having an etch selectivity with respect to the insulating layer.

Abstract: A semiconductor storage device controls writing in a memory unit including an anti-fuse element. The device includes a comparison unit configured to compare, with a reference voltage, a voltage generated across a resistor element connected in series with a power supply line used to energize the anti-fuse element, and a control unit configured to, in writing in the memory unit, control writing in the anti-fuse element of the memory unit based on an output of the comparison unit.

Abstract: A semiconductor memory device with improved performance and reliability is provided. The semiconductor memory device includes a substrate having a cell region and a peripheral region, a cell region isolation layer that separates the cell region from the peripheral region, and a plurality of cell gate structures, each including a cell gate electrode that extends in a first direction. The cell region includes a plurality of active areas that extend in a second direction different from the first direction, and are between a respective cell element isolation layer and the cell region isolation layer. Each of the active areas includes a first portion and a second portion separated by the cell gate structure, the second portion of the active area is on both sides of a respective one of the first portion of the active area. The active areas includes a normal active area and a dummy active area.

Abstract: A manufacturing method of a semiconductor device includes: a first step of forming a laminated film by growing crystals on a sapphire substrate, forming an insulating film on a laminated film, and forming contact holes at an electrical connection point of an n-GaN layer and an electrical connection point of a p-GaN layer in the insulating film to produce a first member; a second step of forming a conductive layer on the first member to produce a second member in which the conductive layer electrically connects the electrical connection point of the n-GaN layer and the electrical connection point of the p-GaN layer; a third step of irradiating the second member with excitation light and measuring light emission generated in the second member; and a fourth step of forming a first pad electrode and a second pad electrode to produce a semiconductor device.

Abstract: A display panel includes a display substrate and a touch function layer. The display substrate includes a substrate, a first barrier wall, an organic structure and a film encapsulation layer. The organic structure is on the substrate and surrounds the first barrier wall. The organic structure includes at least one organic layer. The film encapsulation layer is on a side of the first barrier wall away from the substrate. An inorganic encapsulation layer in the film encapsulation layer covers the first barrier wall. On the substrate, an orthographic projection of the inorganic encapsulation layer is non-overlapping with an orthographic projection of the organic structure. The touch function layer includes an inorganic dielectric layer contacting the film encapsulation layer. The inorganic dielectric layer covers the first barrier wall. On the substrate, an orthographic projection of the inorganic dielectric layer is non-overlapping with the orthographic projection of the organic structure.

Abstract: Molybdenum (Mo) metal-on-metal (MoM) deposition methods for providing true bottom-up fill in vias and/or other gap features in device structures. These device structures contain metal at the bottom surface and have dielectric sidewalls. The deposition process provides molybdenum growth only, in some cases, on the metal film/layer to provide a selective process that can be called a metal-on-metal (MoM) process. The Mo MoM deposition process described herein are not limited to thin films (e.g., films less than 50 ?) and can be used to deposit thicker films (e.g., greater than 50 ? in some cases and greater than 200 ? in other useful cases) on metal surfaces while no, or substantially no, deposition is found on dielectric surfaces.

Abstract: A display substrate, manufacturing method thereof, and display device. In the display substrate, a gate insulating pattern is located at a side of an active layer, a metal conductive layer is at least partially located at a side of the gate insulating pattern. The gate insulating pattern includes a first opening, the active layer includes a second opening, an orthographic projection of the second opening on the base substrate is located within an orthographic projection of the first opening on the base substrate, the metal conductive layer includes a main body part and an extension part, the extension part is electrically connected with the active layer exposed by the first opening, and the conductive structure is overlapped with the extension part, and includes a connection part extending to the second opening and electrically connecting the active layer on two sides of the second opening.

Abstract: A semiconductor device includes peripheral active patterns on a substrate, first and second peripheral trench regions adjacent the peripheral active patterns, a first isolation liner on inner surfaces of the first and second peripheral trench regions, a second isolation liner on the first isolation liner in the first and second peripheral trench regions, and a device isolation layer on the second isolation liner in the first and second peripheral trench regions. The device isolation layer includes a seam therein in the second peripheral trench region. A width of the first peripheral trench region is greater than a width of the second peripheral trench region at a first height corresponding to top surfaces of the peripheral active patterns with respect to the substrate.

Abstract: A method of depositing titanium nitride is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing titanium nitride which utilizes a direct microwave plasma. In some embodiments, the direct microwave plasma has a high plasma density and low ion energy. In some embodiments, the plasma is generated directly above the substrate surface.

Abstract: A method for manufacturing a semiconductor device includes stacking an etch target layer and an etching mask layer on a substrate having first through third regions, forming first photoresist patterns on the etching mask layer in the first and second regions and a second photoresist pattern to completely cover the third mask layer in the third region, etching the etching mask layer using the first and second photoresist patterns as etching masks to form first mask patterns on the first and second regions and a second mask pattern on the third region, forming a filling pattern in a first opening between first mask patterns on the second region, etching the etch target layer using the first and second mask patterns and the filling pattern as etching masks to form first patterns including second openings on the first region and a bulk pattern covering second and third regions of the substrate.

Abstract: A semiconductor device includes a substrate including a cell region and a core/peripheral region, a bit line structure disposed on the substrate of the cell region and including a polysilicon structure, a barrier pattern, a metal pattern and a capping pattern that are stacked on each other, and a gate structure on the substrate of the core/peripheral region, the gate structure including a gate insulation pattern, a polysilicon pattern, a carbon-containing pattern, a barrier structure, a metal pattern and a capping pattern that are stacked on each other.

Abstract: A method for producing a solar cell, including the following steps: a) providing a substrate having a front side and a back side in a deposition apparatus, and b) coating the substrate in situ with two layers, including b1) oxidizing, by exposing the substrate to an oxygen-containing gas and a first plasma, to create an oxide layer and b2) subsequently depositing a silicon layer or SiC layer by exposure to a gas containing silicon, an optional gas containing carbon and a second plasma, wherein step b) is carried out under vacuum in the deposition apparatus and the vacuum is maintained continuously during step b).

Abstract: Each pixel of a display apparatus includes a first transistor, a second transistor connected to a first gate of the first transistor and a data line, a third transistor connected to the first gate of the first transistor and a first voltage line, a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor, and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are disposed on a same layer.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

Abstract: An integrated circuit device including a first cell block on a substrate that includes a first cell area, a first dummy cell area surrounding the first cell area in a plan view, the first dummy cell area including first active regions and second active regions in an outer periphery of the first dummy cell area, the first active regions each having a first size and the second active regions each having a second size larger than the first size, first and second word lines extending in a first direction and alternating with each other in a second direction, each of the first word lines including a first landing area extending between a second active region and a first active region, the first active region being near and apart from the second active region in the second direction, and first word line contacts on the first landing area may be provided.