Abstract: There is provided a plasma vessel in which a process gas is plasma-excited; a substrate process chamber which is in communication with the plasma vessel; a gas supply system supplying the process gas; and a coil installed to wind around an outer periphery of the plasma vessel and supplied with high-frequency power, wherein the coil is installed such that: a distance from an inner periphery of the coil to an inner periphery of the plasma vessel at a predetermined position on the coil is different from a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at another position on the coil; and a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at a position at which an amplitude of a standing wave of a voltage applied to the coil is maximized is maximized.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: A method for forming a precoat film on a metal surface in a chamber before forming a silicon-containing film having an identical composition system with that of the precoat film on a substrate in the chamber using a PECVD method, wherein the precoat film is formed using a PEALD method in which a first gas and a second gas are supplied into the chamber by shifting timing of supply, the PEALD method comprises an adsorption step comprising supplying the first gas into the chamber so that the source gas component adsorbs on the metal surface, a first purge step comprising discharging an excessive source gas component not adsorbed on the metal surface, and a precoat film forming step comprising supplying the second gas into the chamber and applying high-frequency power to generate plasma in the reactant gas component in the second gas.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: According to an embodiment, a wafer (W) includes a layer (EL) to be etched, an organic film (OL), an antireflection film (AL), and a mask (MK1), and a method (MT) according to an embodiment includes a step of performing an etching process on the antireflection film (AL) by using the mask (MK1) with plasma generated in a processing container (12), in the processing container (12) of a plasma processing apparatus (10) in which the wafer (W) is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film (SX) on the surface of the mask (MK1), and steps ST6a to ST7 of etching the antireflection film (AL) by removing the antireflection film (AL) for each atomic layer by using the mask (MK1) on which the protective film (SX) is formed.

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.

Abstract: A method of depositing titanium nitride is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing titanium nitride which utilizes a direct microwave plasma. In some embodiments, the direct microwave plasma has a high plasma density and low ion energy. In some embodiments, the plasma is generated directly above the substrate surface.

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.

Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.

Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a plurality of recesses extending about and radially outward of the plurality of apertures.

Abstract: A light-emitting device or the like with high color reproducibility and high luminous efficiency is achieved. The light-emitting device includes a blue pixel, a green pixel, and a red pixel, and the green pixel includes, in a green-light-emitting layer that emits light, a host material that transports carriers, a fluorescence dopant, which serves as a light emission dopant that contribute to light emission, and a thermally activated assist dopant which is composed of a thermally activated delayed fluorescent material.

Abstract: A curable silicone composition is provided. The curable silicone composition is useful for forming a cured product which inhibits the discoloration of silver electrodes or a silver-plated substrate in an optical semiconductor device due to a sulfur-containing gas. The curable silicone composition comprises at least one type of a crown compound. An optical semiconductor device is also provided. The optical semiconductor device has excellent reliability after a sulfur resistance test, in which an optical semiconductor device on silver electrodes or a silver-plated substrate is sealed, covered, or adhered with a cured product of the curable silicone composition.

Abstract: A small-gap device system, preferably including two or more electrodes and one or more spacers maintaining a gap between two or more of the electrodes. A spacer for a small-gap device system, preferably including a plurality of legs defining a mesh structure. A method of spacer and/or small-gap device fabrication, preferably including: defining lateral features, depositing spacer material, selectively removing spacer material, separating the spacer from a fabrication substrate, and/or assembling the small-gap device.

Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.

Abstract: Methods for forming hafnium oxide within a three-dimensional structure, such as in a high aspect ratio hole, are provided. The methods may include depositing a first hafnium-containing material, such as hafnium nitride or hafnium carbide, in a three-dimensional structure and subsequently converting the first hafnium-containing material to a second hafnium-containing material comprising hafnium oxide by exposing the first hafnium-containing material to an oxygen reactant. The volume of the second hafnium-containing material may be greater than that of the first hafnium-containing material. Voids or seams formed during the deposition of the first hafnium-containing material in the three-dimensional structure may be filled by the expanded material after exposing the first hafnium-containing material to the oxygen reactant. Thus, the three-dimensional structure, such as a high aspect ratio hole, can be filled with hafnium oxide substantially free of voids or seams.

Abstract: A packaging structure includes: a substrate provided with a through-cavity penetrating up and down, and a metal heat sink on a front surface of the substrate; a bonding chip mounting area and a first passive element mounting area on the front surface, and a flip chip mounting area, a second passive element mounting area and a pin lead mounting area are provided on a back surface of the substrate; a first sealing ring located at the periphery of the bonding chip mounting area and the first passive element mounting area; a first cover plate packaged on the first sealing ring; a second sealing ring located at the periphery of the flip chip mounting area and the second passive element mounting area with the pin lead mounting area being located at the periphery of the second sealing ring; and a second cover plate packaged on the second sealing ring.

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said first transistors controls power delivery for at least one of said second transistor, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

Abstract: A circuit board assembly includes a circuit board, an electronic surface mount device (SMD), and a spacer that attaches the SMD to the circuit board. A coefficient of thermal expansion (CTE) of the spacer is closer to a CTE of the SMD than a CTE of the circuit board. The circuit board assembly also includes a flexible electrical lead that extends between and that is electrically connected to the SMD and the electrical node of the circuit board. Methods of manufacturing the circuit board assembly include selectively heating joining material at a predetermined heating rate and selectively cooling the joining material at a predetermined cooling rate to attach the flexible electrical leads to the SMD and the circuit board.