Abstract: A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.

Abstract: A semiconductor processing device is disclosed. The device can include a reactor and a solid source vessel configured to supply a vaporized solid reactant to the reactor. A process control chamber can be disposed between the solid source vessel and the reactor. The device can include a valve upstream of the process control chamber. A control system can be configured to control operation of the valve based at least in part on feedback of measured pressure in the process control chamber.

Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.

Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate to a first temperature while supporting the substrate on a substrate support, and supplying a process gas into a process vessel accommodating the substrate support; (b) lowering a temperature of a low temperature structure provided in the process vessel to a second temperature lower than the first temperature by supplying an inert gas or air to a coolant flow path provided in the process vessel after (a) for a predetermined time, wherein defects occur when a cleaning gas is supplied to the low temperature structure at the first temperature; and (c) cleaning the low temperature structure by supplying the cleaning gas into the process vessel after (b).

Abstract: A laser annealing method performed on a reflective photomask may include preparing a reflective photomask including a pattern area and a border area surrounding the pattern area and irradiating a laser beam onto the border area of the reflective photomask. The irradiating of the laser beam may include split-irradiating a plurality of laser beam spots onto the border area. Each of the plurality of laser beam spots may be shaped using a beam shaper. The beam shaper may include a blind area, a transparent area at a center of the blind area, and a semitransparent area between the blind area and the transparent area. Each of the plurality of laser beam spots may include a center portion passing through the transparent area and having a uniform energy profile and an edge portion passing through the semitransparent area and having an inclined energy profile.

Abstract: There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.

Abstract: A thermionic energy conversion system, preferably including one or more electron collectors, interfacial layers, encapsulation, and/or electron emitters. A method for manufacturing the thermionic energy conversion system. A method of operation for a thermionic energy conversion system, preferably including receiving power, emitting electrons, and receiving the emitted electrons, and optionally including convectively transferring heat.

Abstract: A display device may include: a substrate including a display area and a non-display area; and pixels in the display area, and each including sub-pixels. Each sub-pixel may include a pixel circuit layer, and a display element layer including at least one light emitting element. The display element layer may include: a first electrode on the pixel circuit layer; a second electrode on the first electrode and electrically insulated from the first electrode; the light emitting element including a first end portion coupled to the first electrode and a second end portion coupled to the second electrode, and between the first electrode and the second electrode; an intermediate layer enclosing at least one area of the light emitting element, and on the first electrode; a connection line electrically connected to the second electrode. The second electrode may be on the intermediate layer.

Abstract: A display panel includes a drive backplane, a transparent insulating layer and a light-emitting device layer. The drive backplane includes a driving circuit layer, a metal wiring layer, a first insulating layer and a reflective electrode layer. The first insulating layer has first via holes filled with first metal connectors. The reflective electrode layer includes first reflective electrodes respectively connected with the metal wiring layer through the first metal connectors. The light-emitting device layer includes a pixel electrode layer, an organic light-emitting layer and a common electrode layer. The pixel electrode layer includes first pixel electrodes respectively connected with the first reflective electrodes through the connection via holes. A distance between an orthographic projection of the connection via hole on the pixel electrode layer and an edge of the first pixel electrode is not less than a first threshold value.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

Abstract: The present application discloses a display panel and a display device. The display panel includes pixel areas and transmitting areas in a first display area. The display panel further includes a light-emitting unit layer including light-emitting units, an auxiliary layer, a first electrode layer covering the light-emitting unit layer and at least part of the auxiliary layer, and a transparent auxiliary electrode layer at least covering part of the auxiliary layer and electrically connected to the first electrode layer. A thickness of the first electrode layer on the auxiliary layer is less than a thickness of the first electrode layer on the light-emitting unit layer.

Abstract: A light emitting module including a mounting substrate, light emitting chips mounted on the mounting substrate, and pads, in which the light emitting chips include a first substrate, a first light emitting unit on a first surface of the first substrate, a second substrate spaced apart from the first substrate, and a second light emitting unit on a second surface of the second substrate, the first substrate includes a first side surface including a first modified surface, and the second substrate includes a second side surface facing the first side surface and including a second modified surface, the first modified surface includes first modified regions extended in a thickness direction and first ruptured regions disposed therebetween, the second modified surface includes second modified regions extended in the thickness direction and second ruptured regions disposed therebetween, and the first ruptured regions have the same width as the second ruptured regions.

Abstract: In an embodiment, a system includes: a base; and a rod set comprising multiple rods connected to the base, wherein each rod of the rod set comprises multiple fingers disposed in a vertically-stacked relationship to each other and separated respectively from each other by respective slots, wherein each slot is configured to receive a bevel of a wafer, and wherein each of the multiple fingers comprises a rounded end at a furthest extension.

Abstract: Generally, examples described herein relate to methods and processing systems for performing multiple processes in a same processing chamber on a flowable gap-fill film deposited on a substrate. In an example, a semiconductor processing system includes a processing chamber and a system controller. The system controller includes a processor and memory. The memory stores instructions, that when executed by the processor cause the system controller to: control a first process within the processing chamber performed on a substrate having thereon a film deposited by a flowable process, and control a second process within the process chamber performed on the substrate having thereon the film. The first process includes stabilizing bonds in the film to form a stabilized film. The second process includes densifying the stabilized film.

Abstract: Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.

Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

Abstract: The present disclosure relates to a display panel. The display panel may include a substrate. The substrate may include a display area, a dummy area inside the display area, and a boundary area between the dummy area and the display area on the substrate. The display substrate may further include an isolation protrusion on the substrate at the boundary area. The isolation protrusion may be configured to isolate a functional layer in the display area from the functional layer in the dummy area, and at least a side surface of the isolation protrusion facing the dummy area may be covered by an isolation inorganic layer.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: A light-collecting unit having an inverted pyramid shape is described. The light-collecting unit has one or more outer light-collecting panel facing inward. The light-collecting unit also includes a first plurality of inner, light-collecting panels facing outward and a second plurality of inner, light-collecting panels facing inward. A flower base is configured to support the first plurality of inner, light-collecting panels and the second plurality of inner, light-collecting panels. The first plurality of inner, light-collecting panels is disposed on an outer facing side of the flower base and the second plurality of inner, light-collecting panels is disposed on an inner facing side of the flower base. The light-collecting unit may also include a light emitting element, such as an LED or fiber optic cable end. The light emitting element may provide infrared light to the light-collecting unit. The light emitting element may provide the light using pulse-wave modulation.

Abstract: A sealing resin composition contains an epoxy resin (A), a curing agent (B) having at least one amino group in one molecule, and an inorganic filler (C), wherein the inorganic filler (C) contains a first inorganic filler (C1) having an average particle size from 0.1 ?m to 20 ?m and a second inorganic filler (C2) having an average particle size from 10 nm to 80 nm, and a value obtained by multiplying a specific surface area of the inorganic filler (C), by a proportion of a mass of the inorganic filler (C) in a solid mass of the sealing resin composition, is 4.0 m2/g or more.