Abstract: The present disclosure provides a method for cleaning a vacuum system used in the manufacture of OLED devices. The method includes performing pre-cleaning for cleaning at least a portion of the vacuum system, and performing plasma cleaning using a remote plasma source.

Abstract: Disclosed herein is a full-size mask assembly and a manufacturing method thereof. The full-size mask assembly according to an embodiment of the present invention includes a frame having a frame opening formed therein and a support surrounding the frame opening, a structural auxiliary mask supported by the support and having a plurality of shafts in a grid shape to form a plurality of structural auxiliary mask openings, and a plurality of cell unit masks supported by the structural auxiliary mask and each of which has a deposition pattern portion through which a deposition material passes.

Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

Abstract: Disclosed herein is a full-size mask assembly and a manufacturing method thereof. The full-size mask assembly according to an embodiment of the present invention includes a frame having a frame opening formed therein and a support surrounding the frame opening, a structural auxiliary mask supported by the support and having a plurality of shafts in a grid shape to form a plurality of structural auxiliary mask openings, and a plurality of cell unit masks supported by the structural auxiliary mask and each of which has a deposition pattern portion through which a deposition material passes.

Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, an underfill material with improved surface coverage is provided between adjacent pixels of a pixelated-LED chip. The underfill material may be arranged to cover all lateral surfaces between the adjacent pixels. In some aspects, discontinuous substrate portions are formed before application of underfill materials. In some aspects, a wetting layer is provided to improve wicking or flow of underfill materials during various fabrication steps.

Abstract: A method for producing a semiconductor component is proposed. The method includes providing a housing. At least one semiconductor chip is arranged in a cavity of the housing. Furthermore, an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire. The method furthermore includes applying a protective material on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing. Moreover, the method also includes filling at least one partial region of the cavity with a gel.

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.

Abstract: Various methods and apparatuses are disclosed. A method may include disposing at least one die on a location on a carrier substrate, forming at least one stud bump on each of at least one die, forming a phosphor layer on the at least one stud bump and the at least one die, removing a top portion of the phosphor layer to expose the at least one stud bump, and removing a side portion of the phosphor layer located between two adjacent dies. An apparatus may include a die comprising top, bottom, and side surfaces. A phosphor layer may be disposed on the top, bottom, and side surfaces of the die. The phosphor layer may have substantially equal thicknesses on the top and side surfaces of the die as well as one or more stud bumps disposed on the top surface of the die.

Abstract: A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

Abstract: There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

Abstract: Embodiments reduce or eliminate microbridge defects in extreme ultraviolet (EUV) patterning for microelectronic workpieces. A patterned layer is formed over a multilayer structure using an EUV patterning process. Protective material is then deposited over the patterned layer using one or more oblique deposition processes. One or more material bridges extending between line patterns within the patterned layer are then removed while using the protective material to protect the line patterns. As such, microbridge defects caused in prior solutions are reduced or eliminated. For one embodiment, the oblique deposition processes include physical vapor deposition (PVD) processes that apply the same or different protective materials in multiple directions with respect to line patterns within the patterned layer. For one embodiment, the removing includes one or more plasma trim processes. Variations can be implemented.

Abstract: A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

Abstract: A processing method of a wafer in which a modified layer is formed inside the wafer. In the processing method, irradiation with a first laser beam is executed from a back surface side of the wafer and the modified layer is formed inside the wafer. Then, irradiation with a second laser beam is executed with the focal point thereof positioned to the inside or the front surface of the wafer and reflected light is imaged by an imaging unit. Furthermore, a processing state of the wafer is determined on the basis of a taken image. The second laser beam is shaped in such a manner that a sectional shape thereof in a surface perpendicular to a traveling direction thereof becomes asymmetric across the modified layer.

Abstract: A packaged electronic device includes a multilayer lead frame having first and second trace levels, a via level therebetween, a conductive feed structure, and a conductive reflector wall. The first trace level includes a conductive coupler antenna and a conductive ground structure that extends in a plane of orthogonal first and second directions, and a portion of the conductive coupler antenna faces outward along a third direction orthogonal to the first and second directions. The conductive reflector wall has an opening and extends along the third direction between the first and second trace levels around a portion of the conductive coupler antenna. The conductive feed structure is coupled to the conductive coupler antenna and extends along the first direction through the opening of the conductive reflector wall.

Abstract: There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.

Abstract: A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated by particle bombardment which is configured to remove atoms of the first hybrid interface layer and atoms of the second hybrid interface layer to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.

Abstract: A light emitting device includes a substrate including a base member including a front surface, a rear surface opposite to the front surface, a bottom surface perpendicular to the front surface, and a top surface opposite to the bottom surface, a first wiring portion located on the front surface, and a second wiring portion located on the rear surface; a light emitting element electrically connected with the first wiring portion; and a first reflective member covering a lateral surface of the light emitting element and the front surface of the base member. The base member has a recessed portion opened on the rear surface and the bottom surface. The substrate includes a third wiring portion covering an inner wall of the recessed portion and electrically connected with the second wiring portion, and a via in contact with the first wiring portion, the second wiring portion and the third wiring portion.

Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate to a first temperature while supporting the substrate on a substrate support, and supplying a process gas into a process vessel accommodating the substrate support; (b) lowering a temperature of a low temperature structure provided in the process vessel to a second temperature lower than the first temperature by supplying an inert gas or air to a coolant flow path provided in the process vessel after (a) for a predetermined time, wherein defects occur when a cleaning gas is supplied to the low temperature structure at the first temperature; and (c) cleaning the low temperature structure by supplying the cleaning gas into the process vessel after (b).