Patents Examined by Brook Kebede
  • Patent number: 10797024
    Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.
    Type: Grant
    Filed: March 21, 2020
    Date of Patent: October 6, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, YongMin Kim, JaeHyuk Choi, YeoChan Ko, HeeSoo Lee
  • Patent number: 10797195
    Abstract: The invention relates to semiconductor devices for converting ionizing radiation into an electrical signal. The present ionizing radiation sensor has an n+-i-p+ structure, produced using the planar process. The sensor contains an i-region in the form of a high-resistivity substrate of high-purity float-zone silicon with p-type conductivity, having on its front face n+-regions (2, 3), an SiO2 layer (4), aluminium metallization (5), and a passivation layer. On the front face of the substrate (1) n-regions (2) are formed by ion implantation; a masking layer of SiO2 (layer 4) is grown; aluminium metallization (5) is deposited; and a passivation layer (6) is applied.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 6, 2020
    Inventors: Vladimir Aleksandrovich Elin, Mikhail Moiseevich Merkin
  • Patent number: 10790416
    Abstract: Various methods and apparatuses are disclosed. A method may include disposing at least one die on a location on a carrier substrate, forming at least one stud bump on each of at least one die, forming a phosphor layer on the at least one stud bump and the at least one die, removing a top portion of the phosphor layer to expose the at least one stud bump, and removing a side portion of the phosphor layer located between two adjacent dies. An apparatus may include a die comprising top, bottom, and side surfaces. A phosphor layer may be disposed on the top, bottom, and side surfaces of the die. The phosphor layer may have substantially equal thicknesses on the top and side surfaces of the die as well as one or more stud bumps disposed on the top surface of the die.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 29, 2020
    Assignee: BRIDGELUX INC.
    Inventors: Babak Imangholi, Khashayar Phil Oliaei, Scott West
  • Patent number: 10790305
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-Boong Lee, Jong-Hoon Jung
  • Patent number: 10790268
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A first encapsulant is deposited over the first substrate and semiconductor die after forming the conductive pillar. A groove is formed in the first encapsulant around the conductive pillar. A first passive device is disposed over a second substrate. A second encapsulant is deposited over the first passive device and second substrate. The first substrate is mounted over the second substrate. A shielding layer is formed over the second encapsulant. A second passive device can be mounted over the second substrate opposite the first passive device and outside a footprint of the first substrate.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 29, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee
  • Patent number: 10784231
    Abstract: The present invention addresses the problem of enlarging a sensing area in an ultrasonic probe so as to achieve a higher definition. This ultrasonic diagnostic equipment is provided with an ultrasonic probe that comprises: a CMUT chip (2a) that has drive electrodes (3e)-(3j), etc., arranged in a grid-like configuration on a rectangular CMUT element section (21); and a CMUT chip (2b) that has drive electrodes (3p)-(3u), etc., arranged in a grid-like configuration on the rectangular CMUT element section (21), that is adjacent to the CMUT chip (2a), and in which the drive electrodes (3e)-(3j) of the adjacent CMUT chip (2a) are electrically connected to the respective drive electrodes (3p)-(3u) via bonding wires (4f)-(4i), etc.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 22, 2020
    Assignee: HITACHI, LTD.
    Inventors: Yasuhiro Yoshimura, Akifumi Sako, Naoaki Yamashita, Tatsuya Nagata
  • Patent number: 10784563
    Abstract: Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiaoxiong Gu, Wooram Lee, Duixian Liu, Christian Wilhelmus Baks, Alberto Valdes-Garcia
  • Patent number: 10777496
    Abstract: The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Luca Del Carro, Jonas Z├╝rcher
  • Patent number: 10777662
    Abstract: The present disclosure provides a manufacturing method of a thin film transistor, including: selecting a substrate, and forming a bottom gate, a gate insulating layer and a source-drain above the selected substrate, wherein the bottom gate and the source-drain adopts a conductive metal oxide with an adjustable work function as a metal conducting electrode; rinsing and drying the source-drain of the selected substrate, and ozone cleaning dried source-drain for a predetermined time under a predetermined illumination condition, bombarding the source-drain with oxygen plasma for a period of time, forming an active layer made of a carbon material over the source-drain; forming a passivation layer over the active layer. The implementation of the disclosure can reduce the contact resistance and improve the performance of the carbon-based thin film transistor device by adjusting the work function of the contact surface between the conductive metal and the active layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 15, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 10770348
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo
  • Patent number: 10770535
    Abstract: A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: September 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yang Wan Kim, Ji Hyun Ka, Tae Hoon Kwon, Byung Sun Kim, Hyung Jun Park, Su Jin Lee, Jae Yong Lee, Jin Tae Jeong, Seung Ji Cha
  • Patent number: 10763269
    Abstract: An anti-fuse cell includes a control device and an anti-fuse element is introduced. The control device includes a source node, a drain node and a gate node, wherein the gate node is electrically coupled to a word line and the drain node is electrically coupled to a bit line. The anti-fuse element includes a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer of the anti-fuse element is physically stacked upon a conductive layer and electrically connected to the source node of the control device, and first conductive layer is electrically coupled to a program line through a via. An anti-fuse cell having multiple anti-fuse elements and a chip having a plurality of anti-fuse cells are also introduced.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10763123
    Abstract: In an embodiment, a wafer W includes a layer EL to be etched and a mask MK4 provided on the layer EL to be etched, and a method MT of an embodiment, the layer EL to be etched is etched by removing the layer EL to be etched for each atomic layer, by repeating sequence SQ3 including step ST9a of irradiating the mask MK4 with secondary electrons by generating plasma and applying a DC voltage to an upper electrode 30 of a parallel plate electrode, and covering the mask MK4 with silicon oxide compound, step ST9b of generating plasma of fluorocarbon-based gas and forming a mixed layer MX2 including radicals on an atomic layer of the layer EL to be etched, and ST9d of generating plasma of Ar gas and applying a bias voltage to remove the mixed layer MX2.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu
  • Patent number: 10756249
    Abstract: A method is provided for producing an electrically-powered device and/or component that is embeddable in a solid structural component, and a system, a produced device and/or a produced component is provided. The produced electrically powered device includes an attached autonomous electrical power source in a form of a unique, environmentally-friendly structure configured to transform thermal energy at any temperature above absolute zero to an electric potential without any external stimulus including physical movement or deformation energy. The autonomous electrical power source component provides a mechanism for generating renewable energy as primary power for the electrically-powered device and/or component once an integrated structure including the device and/or component is deployed in an environment that restricts future access to the electrical power source for servicing, recharge, replacement, replenishment or the like.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 25, 2020
    Assignee: FACE INTERNATIONAL CORPORATION
    Inventors: Clark D Boyd, Bradbury R Face, Jeffrey D Shepard
  • Patent number: 10756209
    Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Patent number: 10756031
    Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Franklin M. Baez, Brian W. Quinlan, Charles L. Reynolds, Krishna R. Tunga, Thomas Weiss
  • Patent number: 10727387
    Abstract: Alight emitting device includes a substrate including a base member including a front surface, a rear surface opposite to the front surface, a bottom surface perpendicular to the front surface, and a top surface opposite to the bottom surface, a first wiring portion located on the front surface, and a second wiring portion located on the rear surface; a light emitting element electrically connected with the first wiring portion; and a first reflective member covering a lateral surface of the light emitting element and the front surface of the base member. The base member has a recessed portion opened on the rear surface and the bottom surface. The substrate includes a third wiring portion covering an inner wall of the recessed portion and electrically connected with the second wiring portion, and a via in contact with the first wiring portion, the second wiring portion and the third wiring portion.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 28, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Gensui Tamura
  • Patent number: 10729006
    Abstract: [Objective] To provide a wiring substrate for electronic component inspection apparatus which includes a first laminate of resin layers with a plurality of pads for probe provided on its front surface and a second laminate of ceramic layers disposed on the back side of the first laminate and which, despite joining by brazing of a plurality of studs to the back surface of the second laminate, is free from deformation of resin of the first laminate caused by softening or the like and from accidental formation of a short circuit between brazing material layers used for the brazing and external connection terminals formed on the back surface of the second laminate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 28, 2020
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takakuni Nasu, Yousuke Kondo, Kouta Kimata, Guangzhu Jin
  • Patent number: 10727219
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 10721845
    Abstract: Disclosed is a system and method for optimizing cooling efficiency of a data center is disclosed. The system may comprise an importing module, a Computational fluid dynamics (CFD) modeling module, a scope determination module, a metrics computation module, an identification module and a recommendation module. The importing module may be configured to import data associated to the data center. The CFD modeling module may be configured to leverage an external CFD Analysis tool in order to develop a CFD model of the data center. The scope determination module may be configured to determine a scope for optimizing the cooling efficiency of the data center. The metrics computation module may be configured to compute metrics based upon the data. The identification module may be configured to identify inefficiency and a cause producing the inefficiency. The recommendation module may be configured to facilitate optimizing cooling efficiency of the data center.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 21, 2020
    Assignee: Tata Consultancy Services Limited
    Inventors: Harshad Girish Bhagwat, Umesh Singh, Sankara Narayanan D, Arun Varghese, Amarendra Kumar Singh, Rajesh Jayaprakash, Anand Sivasubramaniam