Abstract: A method and apparatus for on-line measurement of the wafer thinning and grinding force, related to the field of ultra-precision machining of semiconductor wafer materials. The grinding force measuring apparatus comprises a semiconductor wafer, a worktable, a bearing table, a thin film pressure sensor, and a data processing and wireless transmission module. The grinding force measuring method includes sensor calibration based on the testing device and on-line measurement of grinding force. Using the grinding force measuring device and method provided by the invention, the grinding force in the semiconductor wafer grinding process can be monitored in real time, which is of great significance for semiconductor processing and reducing grinding damage.

Abstract: Provided are a composition for depositing a silicon-containing thin film containing a bis(aminosilyl)alkylamine compound and a method for manufacturing a silicon-containing thin film using the same, and more particularly, a composition for depositing a silicon-containing thin film, containing the bis(aminosilyl)alkylamine compound capable of being usefully used as a precursor of the silicon-containing thin film, and a method for manufacturing a silicon-containing thin film using the same.

Abstract: Transition metal dichalcogenides (TMDs) are deposited by atomic layer deposition as thin layers on a substrate. The TMDs may be grown on oxide substrates and may have a tunable TMD-oxide interface. The TMD may be etched using an atomic layer etching technique.

Abstract: A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed.

Abstract: Certain embodiments of the invention utilize low temperature atomic layer deposition methodology to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses silicon tetraiodide (SiI4) or disilicon hexaiodide (Si2I6) as one precursor and uses a nitrogen-containing material such as ammonia as another precursor. In circumstances where a selective deposition of silicon nitride is desired to be deposited over silicon dioxide, the substrate surface is first treated with ammonia plasma.

Abstract: Provided are an imaging device that is inconspicuous from the outside, can easily apply design, and can obtain a clear image, and a laminate. The imaging device includes: an imaging unit that includes an image pickup element; and a transflective film that is disposed on a side of the imaging unit where light is incident into the image pickup element and reflects a part of the incident light, in which the transflective film includes at least one of a cholesteric liquid crystal layer or a multi-layer polymer film, when seen from a direction perpendicular to a surface of the image pickup element where light is incident, a peripheral region surrounding the imaging unit satisfies L*?50 in a CIE-Lab (D50) color space, and when seen from the direction perpendicular to the surface of the image pickup element where light is incident, the transflective film is disposed to cover at least the imaging unit and the peripheral region.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.

Abstract: The present invention relates to a device comprising physical properties controlled by a microstructure and a method of manufacturing the same. The present invention discloses a base layer having a patterned surface; and a two-dimensional structure layer formed on the patterned surface of the base layer, the two-dimensional structure layer extending on and in compliance to topography of the patterned surface of the base layer, such that change of physical properties of the two-dimensional structure layer conforms to the stress generated along the topography.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).

Abstract: A method for processing a transparent workpiece includes generating a beam of radiation and forming a defect in or on an object. The beam is a quasi-non-diffracting beam and has a focal volume. Forming the defect includes directing the beam onto the object and positioning the focal volume partially or fully within the object. Generating the beam includes partially blocking the beam upstream of the focal volume to adjust an axial symmetry of the freeform energy distribution with respect to an optical axis of the beam using an adjustable blocking element and/or spatially modulating a phase of the beam upstream of the focal volume to adjust a geometry of the freeform energy distribution using a phase mask. The freeform energy distribution has energy sufficient to induce multi-photon absorption in a region of the object that is co-located with the focal volume. The induced multi-photon absorption produces the defect.

Abstract: An array substrate may include a dielectric layer (1), a plurality of pixel units (2) on the dielectric layer (1), auxiliary light emitting elements (3), and a fingerprint recognition layer (4) on a side of the dielectric layer (1) opposite from the pixel units (2). Each of the pixel units (2) may comprise transparent display elements (21). The fingerprint recognition layer (4) may comprise fingerprint recognition elements (41). The fingerprint recognition elements (41) may be configured to receive light emitted by the auxiliary light emitting elements (3) and reflected by a touch control body (10) to identify fingerprint information.

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.

Abstract: A laser irradiation apparatus includes: a laser module configured to emit a laser beam; a first optical system configured to scan the laser beam emitted from the laser module along a first direction; an optical element configured to refract the laser beam emitted from the first optical system; and a substrate supporter on which a base substrate to which the laser beam refracted through the optical element reaches is arranged.

Abstract: A semiconductor package includes a lead frame, a semiconductor chip, a plurality of three-dimensional wrings, and a mold resin. The semiconductor chip is mounted on the lead frame. The mold resin covers a part of the lead frame, the semiconductor chip, and a part of each of the plurality of three-dimensional wirings.

Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.

Abstract: The disclosure provides a method to optimize atomic layer deposition comprising the following steps: (A) providing a cellulose nanofiber; (B) acidifying the cellulose nanofiber by an acidifying treatment agent; (C) hydrophobing the acidified cellulose nanofiber by a hydrophobinghydrophobic treatment agent; (D) dissolving the acidified and hydrophobed cellulose nanofiber in a solvent to form a cellulose nanofiber solution; (E) coating the cellulose nanofiber solution on a silicone resin film; (F) heating the coated silicone resin film to form a cellulose nanofiber layer on a surface of the silicone resin film; and (G) forming an inorganic coating layer on the surface of the silicone resin film having the cellulose nanofiber layer by atomic layer deposition.

Abstract: Processes of selectively depositing a metal-containing film comprise: providing a surface having a plurality of materials exposed thereon simultaneously, and exposing the surface to a vapor of a metal-containing film-forming composition that contains a precursor having the formula: LxM(—N(R)—(CR?2)n—NR?2) wherein M is a Group 12, Group 13, Group 14, Group 15, Group IV or Group V element; x+1 is the oxidation state of the M; L is an anionic ligand, independently selected from dialkylamine, alkoxy, alkylimine, bis(trialkylsilylamine), amidinate, betadiketonate, keto-imine, halide, or the like; R, R? each are independently a C1-C10 linear, branched or cyclic alkyl, alkenyl, or trialkylsilyl group; R? is H or a C1-C10 linear, branched or cyclic alkyl, alkenyl or trialkylsilyl group; n=1-4, wherein at least one of the materials is at least partially blocked by a blocking agent from the deposition of the metal-containing film through a vapor deposition process.

Abstract: Disclosed is a method of laser irradiation of a patterned semiconductor device including a periodic array of sub-wavelength fin-like structures, all fin-like structures upstanding from a base face of the semiconductor device and defining an upper face of the periodic array opposite the base face, each fin-like structure having: a width along a first direction parallel to the base face of the order of magnitude or smaller than the laser wavelength; a length along a second direction parallel to the base face and perpendicular to the first direction at least 3 times greater than the width; and a height along a third direction perpendicular to the base face. The method includes: generating a UV pulsed laser beam using a laser module; and irradiating at least a portion of the upper face with the laser beam.

Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.

Abstract: The array substrate of embodiments of the present invention uses the adjustment dielectric layer to reduce parasitic capacitance between the gate metal layer and the electrode layer, thus avoiding the dark streak phenomenon due to the fringing electric field and the surrounding environment and improving display quality.