Patents Examined by Bryan Junge
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Patent number: 10199230Abstract: Methods for selectively depositing a metal silicide layer are provided herein.Type: GrantFiled: July 2, 2015Date of Patent: February 5, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Seshadri Ganguli, Yixiong Yang, Bhushan N. Zope, Xinyu Fu, Avgerinos V. Gelatos, Guoqiang Jian, Bo Zheng
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Patent number: 10166749Abstract: [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles.Type: GrantFiled: January 30, 2012Date of Patent: January 1, 2019Assignees: LAN TECHNICAL SERVICE CO., LTD., TADATOMO SUGAInventors: Tadatomo Suga, Akira Yamauchi, Ryuichi Kondou, Yoshiie Matsumoto
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Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
Patent number: 10170476Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.Type: GrantFiled: October 10, 2017Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Phillip F. Chapman, David S. Collins, Steven H. Voldman -
Patent number: 10158096Abstract: Disclosed is an organic light emitting device.Type: GrantFiled: May 15, 2015Date of Patent: December 18, 2018Assignee: LG DISPLAY CO., LTD.Inventors: Yeon Keun Lee, Seongsu Jang, Jin Ha Hwang, Young Eun Kim
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Patent number: 10153393Abstract: A light emitting diode including an n-doped InXnGa(1-Xn)N layer and a p-doped InXpGa(1-Xp)N layer, and an active area arranged between the InXnGa(1-Xn)N layer and the InXpGa(1-Xp)N layer including: a first InN layer with a thickness eInN106; a second InN layer with a thickness eInN108; a separating layer arranged between the InN layers and including InXbGa(1-Xb)N and a thickness <3 nm; an InX1Ga(1-X1)N layer arranged between the InXnGa(1-Xn)N layer and the first InN layer; an InX2Ga(1-X2)N layer arranged between the InXpGa(1-Xp)N layer and the second InN layer; wherein the indium compositions Xn, Xp, Xb, X1 and X2 are between 0 and about 0.25, and wherein the thicknesses eInN106 and eInN108 are such that eInN106<eInN108.Type: GrantFiled: August 21, 2014Date of Patent: December 11, 2018Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, ALEDIAInventors: Ivan-Christophe Robin, Amelie Dussaigne
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Patent number: 10141416Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: GrantFiled: August 25, 2017Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
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Patent number: 10134897Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.Type: GrantFiled: October 20, 2015Date of Patent: November 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Zhao-Cheng Chen
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Patent number: 10121790Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.Type: GrantFiled: November 3, 2017Date of Patent: November 6, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung
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Patent number: 10121858Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.Type: GrantFiled: October 30, 2015Date of Patent: November 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Richard Kenneth Oxland, Blandine Duriez, Mark van Dal, Martin Christopher Holland
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Patent number: 10115714Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element, a gel-like silicone that covers an upper surface of the second semiconductor element, and a resin portion that covers the gel-like silicone and the first surface of the first semiconductor element.Type: GrantFiled: February 19, 2016Date of Patent: October 30, 2018Assignee: Kabushiki Kaisha ToshibaInventor: Naoya Takai
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Patent number: 10109742Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height T1 from the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height T2 from the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.Type: GrantFiled: September 30, 2015Date of Patent: October 23, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yuan-Shun Chao, Chih-Pin Tsao, Hou-Yu Chen
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Patent number: 10090193Abstract: Disclosed is an integrated circuit (IC) structure that incorporates stacked pair(s) of field effect transistors (FETs), where each stacked pair has a shared gate. The structure also includes an irregular-shaped buried interconnect that connects source/drain regions that are on opposite sides of the shared gate and at different levels (i.e., a lower FET's source/drain region on one side of the shared gate to an upper FET's source/drain region on the opposite side). Also disclosed is a method for forming the structure by forming, during different process stages, different sections of an irregular-shaped cavity (including sections that expose surfaces of the source/drain regions at issue and a section with sidewalls lined by a dielectric spacer) and filling the different sections with sacrificial material. When all of the sections are completed, the sacrificial material is selectively removed, thereby creating the irregular-shaped cavity. Then, the buried interconnect is formed within the cavity.Type: GrantFiled: November 16, 2017Date of Patent: October 2, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel Chanemougame, Lars Liebmann, Ruilong Xie
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Patent number: 10084135Abstract: An illumination device includes a substrate, a light emitting structure, a sealant, and a laminating board is provided. The light emitting structure includes a first electrode layer, a light emitting layer and a second electrode layer stacked on the substrate sequentially. The sealant covers the light emitting structure. The laminating board is attached to the substrate. The sealant is located between the laminating board and the substrate. The laminating board includes a carrier body, a metal layer and a plurality of pads. The metal layer is exposed at a first surface of the carrier body, is in contact with the sealant and shields an area of the light emitting layer of the light emitting structure. The pads are exposed at the first surface of the carrier body and electrically connected to the first electrode layer and the second electrode layer. The metal layer is electrically isolated from the pads.Type: GrantFiled: November 24, 2015Date of Patent: September 25, 2018Assignee: Industrial Technology Research InstituteInventors: Hsuan-Yu Lin, Hsin-Chu Chen, Wen-Hong Liu, Chao-Feng Sung, Chun-Ting Liu, Je-Ping Hu, Wen-Yung Yeh
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Patent number: 10079322Abstract: In an embodiment of the disclosure, a structure is provided which comprises a silicon substrate and a plurality of necklaces of silicon nanowires which are in direct physical contact with a surface of the silicon substrate, wherein the necklaces cover an area of the silicon substrate.Type: GrantFiled: February 24, 2017Date of Patent: September 18, 2018Assignee: Advanced Silicon Group, Inc.Inventors: Marcie R. Black, Jeffrey B. Miller, Michael Jura, Claire Kearns-McCoy, Joanne Yim, Brian P. Murphy
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Patent number: 10074583Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.Type: GrantFiled: October 30, 2015Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Sayuri Hada, Kuniaki Sueoka
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Patent number: 10069113Abstract: An organic light emitting display device and a fabrication method comprising a touch electrode layer including touch electrodes and touch lines on an upper substrate which are directly formed on the upper substrate to secure a large distance between the touch electrodes and cathode as well as minimize a distance between the upper and lower substrates, thereby widening the viewing angle of an image while reducing a parasitic capacitance.Type: GrantFiled: November 24, 2015Date of Patent: September 4, 2018Assignee: LG Display Co., Ltd.Inventors: BuYeol Lee, NamWook Cho, HyoungSu Kim, JaeMyon Lee
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Patent number: 10068802Abstract: An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.Type: GrantFiled: October 17, 2012Date of Patent: September 4, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ebenezer Eshun, Himadri Sekhar Pal, Amitabh Jain
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Patent number: 10056572Abstract: The present specification relates to an organic light emitting device.Type: GrantFiled: April 30, 2015Date of Patent: August 21, 2018Assignee: LG DISPLAY CO., LTD.Inventors: Young Kyun Moon, Jin Bok Lee, Byung Woo Yoo, Minsoo Kang
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Patent number: 10056288Abstract: A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the active area. The gate trench exposes a sidewall of the active area and a sidewall of the trench isolation region. The sidewall of the trench isolation region includes a void. A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer. A second gate dielectric layer is grown on the sidewall of the active area. A gate is embedded in the gate trench.Type: GrantFiled: August 8, 2017Date of Patent: August 21, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tsuo-Wen Lu, Chin-Wei Wu, Tien-Chen Chan, Ger-Pin Lin, Shu-Yen Chan
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Patent number: 10049969Abstract: An integrated circuit includes a lead frame having a die attach paddle with a slot extending through the die attach paddle from a first surface to a second surface. A plurality of semiconductor die are positioned such that a channel is formed between the first, second, and third semiconductor die and the slot of the die attach paddle. A mold material encloses the plurality of semiconductor die and at least a portion of the lead frame and is disposed in the channel such that the second surface of the die attach paddle is substantially flush with the mold material. A method of forming an integrated circuit is also provided.Type: GrantFiled: June 16, 2017Date of Patent: August 14, 2018Assignee: Allegro MicroSystems, LLCInventor: Shixi Louis Liu