Abstract: In some embodiments, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region having a first concentration, and a first gate. The second transistor includes a second source region in a second bulk region having a second concentration higher than the first concentration. The second source region is connected with the first source region and the first gate.

Abstract: A three-dimensional nonvolatile memory device includes a substrate defined with a slimming region, first and second pass regions on both sides of the slimming region, and a cell region adjacent to the slimming region with the first pass region interposed therebetween; a word line stack including a plurality of word lines stacked over the cell region, the first pass region, and the slimming region of the substrate; first wiring lines extending from the slimming region to the first pass region and electrically coupling some word lines with pass transistors formed in the first pass region of the substrate; and second wiring lines extending from the slimming region to the second pass region and electrically coupling remaining word lines, other than the some word lines, with pass transistors formed in the second pass region of the substrate.

Abstract: Disclosed is a light emitting device. The light emitting device includes a nano-structure, a first semiconductor layer on the nano-structure, an active layer on the first semiconductor layer, and a second conductive semiconductor layer on the active layer. The nano-structure includes a graphene layer disposed under the first semiconductor layer to make contact with the first semiconductor layer; and a plurality of nano-textures extending from a top surface of the graphene layer to the first semiconductor layer and contacted with the first semiconductor layer.

Abstract: Illustratively, a finFET comprises at least one fin, and typically several fins, with a trapping region in or on a substrate at the base of each fin to trap ions produced by radiation incident on the substrate. In one embodiment, the trapping region is an implanted region having a conductivity type opposite that of the substrate. In another, the trapping region is a defect region. In another, the trapping region is an epitaxial region grown on the substrate. The finFET is formed by forming the fin or fins and then forming the trapping region at the base of the fin. Illustratively, the trapping region is formed by implanting in the substrate ions having a conductivity type opposite that of the substrate or by creating defects in the substrate or by epitaxially growing a region or regions having an opposite conductivity type to that of the substrate.

Abstract: A method for manufacturing a semiconductor device includes the following steps. A semiconductor substrate is prepared which has a first main surface and a second main surface opposite to each other. The semiconductor substrate is fixed on an adhesive tape at the first main surface. The semiconductor substrate fixed on the adhesive tape is placed in an accommodating chamber. While maintaining a temperature of the adhesive tape at 100° C. or more, a gas is exhausted from the accommodating chamber. After the step of exhausting the gas from the accommodating chamber, a temperature of the semiconductor substrate is reduced. After the step of reducing the temperature of the semiconductor substrate, an electrode is formed on a second main surface of the semiconductor substrate. In this way, there can be provided a method for manufacturing a semiconductor device so as to achieve reduced contact resistance between a semiconductor substrate and an electrode.

Abstract: According to one embodiment, a method of manufacturing a display device, includes preparing a first substrate formed such that a first resin layer is formed on a first support substrate, preparing a second substrate formed such that a second resin layer is formed on a second support substrate, attaching the first substrate and the second substrate, peeling the second support substrate from the second resin layer by radiating a first laser beam toward the second substrate, mounting a signal supply source on a first mounting portion in a state in which the second resin layer, which is opposed to the first mounting portion, is warped in a direction away from the first mounting portion, and adhering the first resin layer and the second resin layer.

Abstract: A transistor is provided, which includes: a semiconductor growth substrate and a semiconductor thermoelectric effect device, wherein the semiconductor thermoelectric effect device contains a semiconductor compound layer, a metal layer, a heat conducting layer, a thermocouple heat conducting device and a heat sink layer, the semiconductor compound layer is grown on the semiconductor growth substrate, the metal layer is grown on the semiconductor compound layer, the heat conducting layer is grown on the metal layer, the thermocouple heating conducting device is grown on the heat conducting layer, and the heat sink layer is grown on the other side surface of the thermocouple heat conducting device opposite to the heat conducting layer. The thermocouple heating conducting device may further contain power supply arms which are grown on the heat conducting layer and are electrically connected with the thermocouple heat conducting device.

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract: A method of manufacturing a heterogeneous layered structure includes growing a hexagonal boron nitride sheet directly on a metal substrate in a chamber, increasing a temperature of the chamber to about 300° C. to about 1500° C., and forming a graphene sheet on the hexagonal boron nitride sheet by supplying a carbon source into the chamber while thermally treating the hexagonal boron nitride sheet at the increased temperature.

Abstract: Methods for forming a conformal dopant monolayer on a substrate are provided. In one embodiment, a method for forming a semi-conductor device on a substrate includes forming a charged layer on a silicon containing surface disposed on a substrate, wherein the charged layer has a first charge, and forming a dopant monolayer on the charged layer, wherein dopants formed in the dopant monolayer include at least one of a group III or group V atoms.

Abstract: Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening.

Abstract: Provided is a storage cell that makes it possible to improve TMR characteristics, a storage device and a magnetic head that include the storage cell. The storage cell includes a layer structure including a storage layer in which a direction of magnetization is varied in correspondence with information, a magnetization pinned layer having magnetization that is perpendicular to a film surface and serves as a reference of information stored in the storage layer, and an intermediate layer that is provided between the storage layer and the magnetization pinned layer and is made of a nonmagnetic body. Carbon is inserted in the intermediate layer, and feeding a current in a laminating direction of the layer structure allows the direction of magnetization in the storage layer to be varied, to allow information to be recorded in the storage layer.

Abstract: Disclosed is a light emitting device including a substrate, a first conductive semiconductor layer disposed on the substrate, an active layer disposed on the first conductive semiconductor layer, and a second conductive semiconductor layer disposed on the active layer, wherein the first conductive semiconductor layer comprises a first layer provided at the upper surface thereof with a notch, a second layer disposed on the first layer and a third layer disposed on the second layer, wherein the first conductive semiconductor layer further comprises a blocking layer between the first layer and the second layer and the blocking layer is disposed along the notch. The light emitting device can reduce leakage current by dislocation and improve resistance to static electricity.

Abstract: A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principal component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principal component on the oxide film; and forming a second protective film containing carbon on the first protective film.

Abstract: An IGBT device includes a drift region, a collector contact, an injector region, a pair of junction implants, a gate contact, and an emitter contact. The injector region includes a first surface in contact with the collector contact, a second surface opposite the first surface and in contact with the drift region, and at least one bypass region running between the first surface and the second surface. Notably, the at least one bypass region has a charge carrier that is different from that of the injector region. The pair of junction implants is in the drift region along a surface of the drift region opposite the injector region. The gate contact and the emitter contact are on the surface of the drift region opposite the injector region.

Abstract: An optoelectronic component includes at least one first carrier with at least two light emitting diodes, wherein each diode has two electrical connections, each electrical connection is led to a contact area, the contact areas are arranged on an underside of the first carrier, and a second carrier, wherein at least two zener diodes are arranged in the second carrier, the zener diodes have further electrical connections, each further electrical connection is led to a further contact area, the further contact areas are arranged on a top side of the second carrier, the first carrier bears by the underside on the top side of the second carrier and is fixedly connected to the second carrier, and the zener diodes antiparallelly connect to the diodes.

Abstract: A method of manufacturing a semiconductor device that sufficiently activates a deep ion injection layer and fully recovers lattice defects generated in the ion injection process. Laser light pulses are successively emitted to form substantially CW (continuous wave) laser light. This feature of the invention stably performs activation of a deep ion injection layer at about 2 ?s with few defects.

Abstract: An integrated circuit system, and a method of manufacture thereof, includes: an integrated circuit substrate; and a discretized tunable precision resistor having a total resistance including: a resistor body over the integrated circuit substrate, interconnects directly on the resistor body, metal taps directly on the interconnects and at opposing sides of the resistor body, and conductive metal strips over the interconnects, wherein the total resistance is a function of an active resistor length of the resistor body between a pair of the metal taps in contact with two of the conductive metal strips.

Abstract: When an IGBT has a barrier layer 10 that separates an upper body region 8a from a lower body region 8b, conductivity modulation is enhanced and on-resistance decreases. When the IGBT also has a Schottky contact region 6 that extends to reach the barrier layer 10, a diode structure can be obtained. In this case, however, a saturation current increases as well as short circuit resistance decreases. The Schottky contact region 6 is separated from the emitter region 4 by the upper body region 8a. By selecting an impurity concentration in the region 8a, an increase in a saturation current can be avoided. Alternatively, a block structure that prevents a depletion layer extending from the region 6 into the region 8a from joining a depletion layer extending from the region 4 into the region 8a may be provided in an area separating the region 6 from the region 4.

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.