Abstract: An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

Abstract: To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. An electrode is provided over an oxide semiconductor layer A, the oxide semiconductor layer A and the electrode are covered with a layer C, and then heat treatment is performed; thus, oxidation of the electrode which is caused in the heat treatment is prevented. For the layer C, for example, an oxide semiconductor can be used. By covering a side surface of the oxide semiconductor layer A where a channel is formed with the layer C and the oxide semiconductor layer B, diffusion of impurities from the side surface of the oxide semiconductor layer A into the oxide semiconductor layer A is prevented.

Abstract: Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate and an anti-fuse device having a select transistor, a bitline contact, and a split channel transistor. The select transistor includes a select gate structure, a bitline source/drain region, and a shared source/drain region. The bitline contact is disposed over and in electrical communication with the bitline source/drain region. The split channel transistor is in electrical communication with the select transistor through the shared source/drain region. The split channel transistor includes an anti-fuse gate structure having an anti-fuse gate and an anti-fuse dielectric layer and a stepped gate structure disposed between the anti-fuse gate structure and the shared source/drain region and having a stepped gate and a stepped dielectric layer. The stepped dielectric layer has a greater thickness than the anti-fuse dielectric layer.

Abstract: Disclosed herein are a double-side cooling type power module and a producing method thereof. The double-side cooling type power module includes a pair of semiconductor chips disposed between an upper substrate and a lower substrate. The double-side cooling type power module includes output terminal leads configured to be disposed on a lower surface of the upper substrate and each connected to the pair of semiconductor chips, respectively; a plus terminal lead configured to be disposed at one side of an upper surface of the lower substrate to be connected to any one semiconductor chip selected from the pair of semiconductor chips; and a minus terminal lead configured to be disposed at the other side of the upper surface of the lower substrate to be connected to the other semiconductor chip of the pair of semiconductor chips.

Abstract: An object of the present invention is to provide a silicon carbide semiconductor device with which the electric field at the time of switching is relaxed and the element withstand voltage can be enhanced. The distance between the outer peripheral end of a second surface electrode and the inner peripheral end of a field insulation film is smaller than the distance between an outer peripheral end of the second surface electrode and an inner peripheral end of the field insulation film in the case where the electric field strength applied to the outer peripheral lower end of the second surface electrode is calculated so as to become equal to the smallest dielectric breakdown strength among the dielectric breakdown strength of the field insulation film and the dielectric breakdown strength of the surface protective film at the time of switching when the value of dV/dt is greater than or equal to 10 kV/?s.

Abstract: A semiconductor device of a circuit is provided. The circuit is configured to be operated under a power supply. The semiconductor device of the circuit includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region; a first drain region defined by a well and a doped region, wherein the first source region and the doped region are separate by a distance, which is a factor which determines a breakdown voltage of the first transistor, the breakdown voltage being associated with the power supply; and a first gate. The second transistor includes a second source region in a second bulk region, the second source region electrically connected with the first source region and the first gate.

Abstract: Some embodiments include an imaging system. The imaging system includes an active matrix pixel array having a flexible substrate and a pixel. The pixel includes a transistor over the flexible substrate, and the transistor includes multiple active layers having a first active layer and a second active layer over the first active layer. Further, the active matrix pixel array also includes a photodiode over the transistor, and the photodiode includes an N-type layer over the transistor, an I layer over the N-type layer, and a P-type layer over the I layer. Meanwhile, the imaging system also includes a flexible scintillator layer over the active matrix pixel array. Other embodiments of related systems and methods are also disclosed.

Abstract: An electroluminescence display device and manufacturing method thereof are provided. An electroluminescence display device includes a pixel, having: an electroluminescence diode, a driving transistor configured to supply a current to the electroluminescence diode, and a switching transistor configured to switch a signal supplied to the driving transistor, wherein a size of a channel area of the driving transistor is different from a size of a channel area of the switching transistor, and wherein a taper angle deviation of the channel areas of the driving transistor and the switching transistor is less than or equal to 10°.

Abstract: An organic light emitting display device is disclosed, which comprises an anode electrode provided in a light emitting area on a substrate having a plurality of pixels, each pixel including a light emitting area and a transmissive area; an organic light emitting layer on the anode electrode; a cathode electrode on the organic light emitting layer; an auxiliary electrode connected with the cathode electrode; and a connection electrode connected with the anode electrode and provided in the transmissive area of the substrate.

Abstract: A lighting device may include a substrate having a carrier, a first electrical busbar, a second electrical busbar, and an optically functional structure on or above the carrier, wherein the optically functional structure is formed laterally between the first and the second electrical busbar, and a first electrode electrically coupled to the first electrical busbar and/or the second electrical busbar, on or above the carrier, and an organic functional layer structure on or above the first electrode, wherein the organic functional layer structure is formed for converting an electric current into an electromagnetic radiation, and a second electrode on or above the organic functional layer structure. The optically functional structure is formed in such a way that the beam path of the electromagnetic radiation which passes through the substrate and/or the spectrum of the electromagnetic radiation passing through the substrate are/is variable by means of the optically functional structure.

Abstract: Provided is a TFT substrate (substrate); a second electrode (vapor-deposited membrane) that is formed on the TFT substrate and includes a protruding portion; and a sealing membrane provided so as to cover the second electrode, wherein, when ? represents an absolute value of a stress of the sealing membrane, t represents a thickness of the sealing membrane, and P represents a sum of a product of an oblique side length and an oblique side slope in a minute region on an oblique side of the protruding portion, a value of an index N expressed by the expression (N=?·t·P) is less than or equal to 935 MPa·?m2.

Abstract: An embodiment of the present specification provides an organic light emitting device including: a first electrode; a second electrode provided opposite to the first electrode; one or more organic material layers provided between the first electrode and the second electrode; an auxiliary electrode provided in the first electrode; and a short circuit prevention layer provided between the first electrode and the auxiliary electrode, wherein the short circuit prevention layer has a resistance value which is greater at 50 or more ° C. than 25° C. The organic light emitting device controls the amount of leakage current when a short circuit defect occurs, thereby solving a problem where a device does not overall operate. The organic light emitting device stably operates without an increase in the amount of leakage current.

Abstract: A magnetic tunnel junction device and a manufacturing method therefor are provided. The magnetic tunnel junction device comprises: a seed layer having an FCC (001) crystal structure; a first ferromagnetic layer located on the seed layer and having perpendicular magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer and having perpendicular magnetic anisotropy, wherein the first ferromagnetic layer has a BCC (001) crystal structure and does not have boron. Therefore, the magnetic tunnel junction device, which is structurally and thermally more stable, can be provided by using the seed layer configured to assist the crystal growth of a boron-free magnetic layer in a BCC (001) direction and provide perpendicular magnetic anisotropy thereto, that is, W2N or TaN which is a nitrogen-doped metal material having a cubic crystal structure and having a similar lattice constant to that of a magnetic layer material.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.

Abstract: A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode formed of a first doped region in the same column is disposed in the first well region. The second diode formed of a second doped region in the same column is disposed in the second well region. A third doped region having the conductivity type of the first well region is disposed in the first well region and is connected to the reset line of the same column. A fourth doped region having the conductivity type of the second well region is disposed in the second well region and is connected to the bit line of the same column.

Abstract: A TFT, a method for manufacturing the TFT, and an array substrate are disclosed. In the TFT according to the present disclosure, the nano conductive points that are independent from one another are formed in a channel area of the active layer, so that the channel area of the active layer can be divided into a plurality of sub channels that are independent from one another, and an equivalent electric field strength thereof can be increased. The larger the equivalent electric field strength is, the higher the carrier mobility ratio would be, and the larger the saturation current of the TFT would become. Therefore, the TFT with a higher definition and a higher aperture ratio can be manufactured.

Abstract: A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.

Abstract: A display substrate includes an annular package region and a display region inside package region. The package region includes an annular adhering region and a groove region positioned inside and/or outside the adhering region. A groove structure in which water-absorbing material and/or oxygen-absorbing material is provided is formed in the groove region. The display substrate can solve the problems of poor moisture isolation effect and influence of oxygen in the conventional display device. A display device including the display substrate is further provided.

Abstract: In a pixel including a selection transistor, a driver transistor, and a light-emitting element, as the driver transistor, a transistor is used in which a channel is formed in an oxide semiconductor film and its channel length is 0.5 ?m or greater and 4.5 ?m or less. The driver transistor includes a first gate electrode over an oxide semiconductor film and a second gate electrode below the oxide semiconductor film. The first gate electrode and the second gate electrode are electrically connected to each other and overlap with the oxide semiconductor film. Furthermore, in the selection transistor of a pixel, which does not need to have field-effect mobility as high as that of the driver transistor, a channel length is made longer than at least the channel length of the driver transistor.