Abstract: A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns.

Abstract: A method and apparatus for circuit design synthesis are described. An edge flow cost function is implemented to obtain edge flow costs for nodes of a network. A subject graph of the network is then mapped using the edge flow costs.

Abstract: A capacitor-cell is in an integrated circuit that is configured by disposing a plurality of cells on a site that is on a chip and that is provided between a power line and a grounding line in a direction of the power line and grounding line. The capacitor cell is disposed in a remaining region on the site, after the plurality of cells are disposed on the site. The capacitor-cell includes a gate poly for accumulating capacitance extending up to at least one of positions of the power line and the grounding line in a planar quadrangular cell-frame that is set for disposing the plurality of cells on the site.

Abstract: A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5?/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.

Abstract: An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product.

Abstract: A hierarchical design apparatus 1 for a semiconductor integrated circuit includes a hierarchical block placing unit 1-02 which places sets of hierarchical blocks onto a chip; a hierarchical block terminal placing unit 1-03 which places terminals of the hierarchical blocks so that for sets of hierarchical blocks having the same function, the hierarchical blocks coincide with each other in a coordinate of the corresponding terminal; an intra-hierarchical block layout unit 1-06 which executes the individual types of intra-hierarchical-block layout designs, meanwhile executes only a single type of intra-hierarchical-block layout design for the sets of hierarchical blocks having the same function; and a chip layout finishing unit 1-07 which replicates thus-obtained layout patterns, and thereby completing a layout design over the entire chip.

Abstract: A method and system of representing geometrical layout design data having a plurality of polygons in electronic design systems is provided. The method includes extracting topological characteristics data corresponding to one or more polygons to form one or more virtual topological polygon. Each virtual polygon is represented by Scan order (SO), with SO corresponding to order in which the vertices of polygon are encountered by a sweep line moving in predefined direction with a predefined angular orientation. The method further includes determining dimensional data corresponding to each polygon to form one or more sized polygons using one or more virtual topological polygon. Thereafter, the spatial data corresponding to each sized polygon is extracted to instantiate each sized polygon.

Abstract: A charged particle beam writing apparatus which the apparatus includes a first area density calculation unit and a first dimension error calculation unit. The apparatus includes a first dimension calculation unit which calculates a second dimension of a pattern obtained by correcting the first dimension error of the first dimension, a second area density calculation unit which calculates a second area density occupied by the pattern of the second dimension in the predetermined region, a second dimension error calculation unit which calculates a second dimension error caused by the loading effect, a second dimension calculation unit which calculates a third dimension by adding the second dimension error to the second dimension, a judgment unit which judges whether a difference between the first dimension and the third dimension is within a predetermined range, and a writing unit which writes the pattern of the second dimension onto a target workpiece.

Abstract: In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates common to the pair of output cones, are detected. Based on the common output cone, a degree of relation between the input gates is calculated and according to the calculation, the strength of relation is determined for the combination of input gates. The strength of relation for a combination of the input gates is set, the combination being based on a specification of the verification target and corresponding to the combination identified from the implementation description. Whether the strength of relation set and that determined for the identified combination coincide is judged and a result of the judgment is output.

Abstract: A method for modifying a photomask layout includes the following steps. First, a photomask layout having at least an edge is provided. A plurality of evaluation points are positioned on the edge. Then, the photomask layout is interpreted to have an interpreted photomask layout and an interpreted edge pattern. The interpreted edge pattern is formed by interpreting the above-mentioned edge. After that, a shift between the edge and the interpreted edge and corresponding to each of the evaluation points is calculated. Afterwards, a shift gradient between two evaluation points can be derived from the shift. Finally, a number of segments between each two evaluation points can be estimated.

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edges are selected from mask layout data of the lithographic mask. The mask layout data includes polygons distributed over cells, where each polygon has edges. The cells include a center cell, two vertical cells above and below the center cell, and two horizontal cells to the left and right of the center cell. Target edge pairs are selected for determining a manufacturing penalty in making the lithographic mask, in a manner that decreases the computational volume in determining the manufacturing penalty. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs selected. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

Abstract: A behavioral synthesis system has a scheduling unit and a mode control unit. The scheduling unit performs scheduling of a behavioral level description with reference to a resource quantity data indicating resource constraint and a resource delay data indicating delay times of respective resources. A single process described in the behavioral level description is divided into a plurality of description blocks, and a scheduling mode among a plurality of scheduling modes is designated with respect to each of the plurality of description block. The mode control unit refers to a mode designation code that indicates the designated scheduling mode and controls such that the scheduling unit performs the scheduling with respect to each description block in accordance with the designated scheduling mode indicated by the mode designation code.

Abstract: The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed.

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has a number of edges. Each target edge pair is defined by two of the edges of one or more of the polygons. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined. Determining the manufacturing penalty is based on the target edge pairs as selected. Determining the manufacturability of the lithographic mask uses continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.