Abstract: A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule.

Abstract: In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of the reduced full subtractor cell is replicated for all bits of the area-efficient subtractor but for the least significant bit. One of a plurality of netlists of subtractor cells is selected for the least significant bit of the area-efficient subtractor in response to a flex bit.

Abstract: A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.

Abstract: The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.

Abstract: Layout information indicating a layout of circuits on a print circuit board is obtained. With reference to the layout information, a connection portion, which electrically connects a ground pattern of the print circuit board and an external ground of the print circuit board, is specified, and a pin, which is included in a connector laid out on the print circuit board and is connected to the ground pattern, is identified. Then, a discharge route between the pin and connection portion is determined.

Abstract: An information processing apparatus which includes a storage unit having stored a design data denoting layout and connection of a circuit, and a timing constraint data including a clock skew value denoting a delay difference allowed for a clock inputted to a pair of elements; a data read-out unit for reading out the design data and the timing constraint data; a clock skew value acquisition unit for acquiring the clock skew value set in correspondence with the pair of elements in layout in the circuit denoted by the design data from the timing constraint data; and a slack calculation unit for calculating a delay time between the pair of elements on the basis of the design data, and calculating a slack value indicating whether or not the pair of elements meets a predetermined design requirement by utilizing the acquired clock skew value and the calculated delay time with respect to the pair of elements.

Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

Abstract: A cell-based architecture for an integrated circuit that uses at least two categories of cells: cut-gate cells and breaker cells. Cut-gate cells have gates that extend from one boundary of the cell to an opposite boundary of the cell. Cut gate features are located along the boundaries of the cell to indicate locations for cutting the gates during fabrication. Instances of the cut-gate cells are arranged in abutting rows that result in the formation of continuous gate strips during the fabrication process, which are then cut into individual gates with a cut-gate mechanism. Breaker cells have gates that do not extend to the boundaries of the breaker cell. To prevent the continuous gate strips from exceeding design rule requirements, instances of breaker cells are placed at intervals between the rows of cut-gate cell instances to restrict the size of the gate strips.

Abstract: A method for designing a power distribution network (PDN) for a system implementing a target device includes computing a target PDN impedance value for the PDN. For each switching frequency of the target device where an effective PDN impedance value for the PDN is greater than the target PDN impedance value, one or more decoupling capacitors for one or more capacitor types are identified to add to the PDN to drive the effective PDN impedance value below the target PDN value. A selection of decoupling capacitors identified is refined to reduce one or more of a cost of the PDN and space required for implementing the PDN.

Abstract: Logic blocks in a synthesized logic design that have specified inputs are identified by performing a two-pass analysis of the synthesized logic design. A number of levels is specified. A forward linear trace is performed to identify inputs at each level for each logic block, without regard to the specific function of each logic block. A list of potential equivalency points is generated from the forward linear trace. A reverse logical trace is then performed from the potential equivalency points to identify equivalent logic. When no equivalent logic exists, the analysis can specify one or more additional inputs, or one or more missing inputs, to determine whether similar logic exists that could be replicated and modified to achieve the desired function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: An intelligent defect diagnosis method for manufacturing fab is provided. The intelligent defect diagnosis method comprises: receiving pluralities of defect data, design layouts and fabrication data; analyzing the defect data, design layouts, and the fabrication data by a defect analysis system, wherein the analyzing step further contains the sub-steps: segmenting and grouping the design layouts into pluralities of multi-pattern group cells to construct LPG cell based pattern groups; introducing the defect data; segmenting defect image into pluralities of defect and pattern contours; mapping the defect data to each multi-pattern group cell to form the LPG based defect composite pattern group; performing coordinate conversion and pattern match between image contour and design layout for coordinate correction; fulfilling CAA with defect contour, pattern contour and design layout, and obtaining corresponding defect yield; classifying the defect type of defect data through defect image classification analysis.

Abstract: Logic blocks in a synthesized logic design that have specified inputs are identified by performing a two-pass analysis of the synthesized logic design. A number of levels is specified. A forward linear trace is performed to identify inputs at each level for each logic block, without regard to the specific function of each logic block. A list of potential equivalency points is generated from the forward linear trace. A reverse logical trace is then performed from the potential equivalency points to identify equivalent logic. When no equivalent logic exists, the analysis can specify one or more additional inputs, or one or more missing inputs, to determine whether similar logic exists that could be replicated and modified to achieve the desired function.

Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.

Abstract: Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Abstract: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.

Abstract: Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.